SUSS MicroTec Test Systems has received purchase orders for test equipment that will enable the development of next-generation integrated circuits, including CMOS transistor scaling to the 16 nm node and beyond and the investigation of the reliability characteristics of high-k dielectrics. The partnership with SEMATECH, a global consortium of chipmakers, Core Wafer Systems and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, New York, includes advanced 300 mm wafer-level characterization systems with ProbeShield Technology and a cryogenic probe capability system to be installed at CNSE’s Albany NanoTech Complex.
In the drive for commercialization of nanotechnology, new measurement challenges have arisen in characterizing the latest semiconductor devices for generating accurate transistor models, which are the building blocks of next-generation ICs. Traditional I-V and C-V measurements are insufficient to characterize and predict device performance and lifetime of devices and circuits in state-of-the-art technological nodes. Moving forward, advanced and complex measurement techniques are required, which engineers use to accurately extract important data such as S-parameters (high-frequency measurements) and flicker-noise (1/f noise) parameters. The choice of ProbeShield and ASUR Technologies ensures that the engineering staff will remain at the cutting-edge of semiconductor and nanotechnology.
Additionally, the miniaturization of semiconductor devices has driven research on the use of new materials in semiconductor devices. Much of this basic research is carried out at cryogenic temperatures. The SUSS MicroTec cryogenic probe system will enable researchers to characterize new materials, such as high-k stacks and compound semiconductor on silicon, at temperatures down to 4 K in a vacuum of 10