Output Matching Circuits
For the output matching circuit, the ZLoad impedance is increased to reduce the impedance transformation ratio (ITR). A low ITR has a low Q characteristic, a parameter that is inversely proportional to the BW. By ensuring the Q is the same in the output matching circuit for the carrier, peaking amplifier and quarter-wave transformer, the bandwidth is widened (Figure 4).  In this topology, the output capacitance of both the carrier and peaking amplifiers are merged into their output matching circuits. However, this slightly altered topology requires the need for an additional offset line in the output path of the peaking amplifier.
Figure 4: Different Doherty output networks to delivery 8 ohm at Zopt,c and Zopt,p at a center frequency of 1.85 GHz. The network with an unmated Q (left) requires the use of a quarter-wave transformer with a high ITR, narrowing the bandwidth. The matched Q network (right) expands bandwidth with the addition of an offset line [5]Image Link

Another output matching circuit lumped CLC quarter-wave topology aims to remove the conventionally leveraged offset line in the peaking amplifier in order to meet the size constraints for mMIMO applications. Typically, DPAs will include a quarter-wavelength offset line in the carrier amplifier and half-wavelength offset line in the peaking amplifier after the output matching networks for proper load modulation and wideband performance. This replacement is accomplished by instead using a series inductor (Lp1), a shunt inductor (Lp2), and a series capacitor (Cp1) after the peaking amplifier (Figure 5). This way, both the frequency dependent compensation functions that the offset lines provide and the output matching functions can be combined into a more simplified, space-constrained circuit. In this circuit, the impedance at power backoff e2 has a similar frequency characteristic to that of a half-wavelength line that acts as an open stub at the center frequency, is inductive at lower frequencies, and capacitive at high frequencies. Moreover, the impedance of the peaking amplifier at saturation e3 can be transformed into any real impedance lower than the optimal impedance of the peaking amplifier e5

Figure 5: Simulated results (5a) of the impedance looking into the peaking amplifier from the power combinating node at saturation e6 and backoff e7 at different impedance transformation ratios e8 Full schematic diagram (5b) of alternative DPA [4]Image Link

In implementing this topology, the bonding wires connecting the peaking FET and the circuit are included in the value of Lp1 while series bonding wires from the carrier FET is included in the output matching network with Lc1, Lc2 while the offset line is formed by the transmission line TLc1 (Figure 5b). This leads to a 10mm by 6mm package (after molding) that is implemented on a multilayer epoxy substrate. Final drain efficiencies stand at 53.7% and PAE at 44.8%, both at 8 dB backoff, while the peak output power is 45.3 dBm, and gain is 28 dB (at 8 dB backoff).

Lumped LCL Quarter-Wave Topology

Output Network
In a lumped LCL quarter-wave topology (Figure 6 (left)), the output capacitance of both amplifiers is resonated out using a shunt inductor. The impedance of the peaking amplifier is inherently high because of this resonance, eliminating the need for an additional offset line. And, instead of using a quarter-wave transmission line, a high-pass LCL circuit is used to perform the same function. This, however, can be simplified by merging the shunt inductors with its adjacent shunt components (Figure 6 (right)). And, because of the large load impedance of the GaN HEMT, the output load impedance can more readily achieve e9
Figure 6: A ℼ-type low-pass and high-pass circuit (left) is used to replace the quarter-wave transmission line in conventional DPAs, saving on space. This can be further optimized by merging in shunt inductive components (Lp and LT) into a singular inductor (L’T) (right)[3]Image Link
Input Network: 2nd Harmonic Control Circuit
Several iterations utilizing a lumped LCL quarter-wave topology for the output circuit attempt to mitigate the need for the DPD circuit and maximize linearity by instead cancelling the IM3s of the carrier and peaking amplifiers at the output combining point [6]. A high efficiency (up to 70%) can be accomplished by matching the harmonics to the optimum impedances. In some versions, second harmonic input control circuits are realized through a parallel LC network that experiences resonance (open circuit) at the fundamental frequency. This LC network and the bond-wire exhibits capacitive impedance at the second harmonic frequency generates a series resonance for a short-circuit at the second harmonic frequency [3]. Achieving this second harmonic impedance around the short point can improve drain efficiency considerably (Figure 7). A tunable capacitor can also be used at the input of the carrier amplifier for multi-band operation. This way, the capacitor can be tuned IM3 performance can be optimized for dual-band capability [7]
Figure 7: 2nd harmonic control circuit used at the input of a lumped LCL quarter-wave DPA topology. Large drain efficiencies and gain of over e11 and 13.5 dB are achieved respectively at 7.2 dB backoff [6]Image Link

In some lumped LCL topologies, both the input and output include harmonic control circuitry to match the harmonics of the output impedance for the carrier and peaking amplifiers with the optimum impedances for drain efficiency [7].

Quasi-lumped Quarter-wave Topology

The quasi-lumped, quarter-wave architecture compensates for the output capacitance of the carrier and peaking amplifiers incorporating it in a transmission line, ultimately forming an impedance inverter. This way, by choosing the right length and characteristic impedance of the artificial transmission line the output capacitances and the bond-ware capacitance can be absorbed. And, rather than be limited by the bandwidth of the conventional half-wavelength transmission line impedance inverter and the bandwidth of the parallel resonator (inductor) that is typically used to eliminate the output capacitances [2]. However, this asymmetrical DPA design can lead to sensitivity issues due to the difference in output capacitances between the carrier and peaking amplifiers.

Wolfspeed GaN on SiC Integrated Power Amplifiers for mMIMO

There are some general conclusions that can be gleaned from the previous topologies aiming for an integrated DPA approach. They are as follows:

  • The need for a relatively large load impedance
  • The need to achieve an adequate load modulation of the carrier amplifier through a 90o phase circuit
  • The need to achieve a high output impedance in the peaking amplifier to minimize the power leakage to the FET while ensuring a phase relationship with the carrier amplifier

With all of these considerations there is a general challenge of integrating the phase compensation network, input matching and output harmonic control circuit together on the input side of the DPA. On the output side, combining the output matching network for proper load modulation as well as replacing the offset lines and quarter-wave transformer with discrete inductors and capacitors for comparable wideband performance is the design challenge.

Wolfspeed integrated DPAs offer two topologies (Figure 8) [8]:

  • A final stage integrated PA (includes only final stage)
  • Fully integrated PA (includes both driver and final stages)
Figure 8: Final stage integrated PA and fully integrated PA with operation in the S-band and ability to cover 200 MHz and 300MHz IBW 4G LTE and 5 NR signals respectively.  Image Link
Final Stage Integrated PA performance with DPD Linearization
With DPD linearization, a five carrier (5C), 20 MHz LTE signal ― 100 MHz instantaneous bandwidth (IBW) ― with 8 dB PAPR at a center frequency (fo) of 3.55 GHz, an ACLR of -55.1 dBc to -56.5 dBc is achieved. This is accomplished as well as an average output power of 39.5 dBm and a high efficiency performance. A ten carrier (10C), 20 MHz LTE signal (200 MHz IBW) at 8 dB PAPR and at a fo of 3.5 GHz, an ACLR of -50.3 dBc to -51.7 dBc is gained (Figure 9).
Figure 9: ACLR plot for Wolfspeed final stage integrated PA with DPD linearization of 5C, 20 MHz LTE signal with 100 MHz IBW (left) and 10C, 20 MHz LTE signal with 200 MHz IBW (right).  Image Link
Fully Integrated PA Performance with DPD Linearization
The fully integrated PA tested with a 10C, 20 MHz LTE signal (200 MHz IBW) and a PAPR of 8 dB at a 3.5 GHz center frequency yields an ACLR of -49.9 dBc to -50.3 dBc. An average output power of 37.5 dBm with a high efficiency as well (Figure 10). In other words, it is possible to accomplish an integrated DPA with the input and output driver stages as well as the input and output DPA stages within a small form factor to better fit the needs of 5G mMIMO. Moreover, with the right design and optimization, this can be done under a wide bandwidth signal with up to 300 MHz IBW.
Figure 10: ACLR plot for Wolfspeed fully integrated PA with DPD linearization for 10C x 20 MHz LTE signal (200 MHz IBW).  Image Link


The various 5G infrastructure trends have led to tighter design tolerances with advanced radio techniques, higher performance requirements, tighter restrictions, and more integration. There is a general call for a higher degree of modularity, PAs for mMIMO are no exception to this trend, where PAs are expected to achieve both a high linearity and efficiency all within a small form factor. This leads to the need for an integrated DPA where a number of design challenges crop up when both minimizing and combining the input and output circuits of the carrier and peaking amplifiers while achieving broadband performance. The GaN HEMT using the GaN on SiC is a promising candidate for the integrated DPA with several advantages including a wide bandwidth performance and the ability to achieve higher efficiencies than other technologies. Wolfspeed 5G mMIMO GaN on SiC integrated PAs show high linearity and efficiency under wide bandwidth signals ― all within a small form factor.

  1. Seunghoon Jee, et al., “GaN MMIC Broadband Doherty Power Amplifier,” APMC 2013
  2. J. H. Qureshi, et al., “A Wide-Band 20W LMOS Doherty Power Amplifier,” IMS 2010
  3. Hwiseob Lee, et al., “Highly Efficient Fully Integrated GaN-HEMT Doherty Power Amplifier Based on Compact Load Network,” TMTT 2017
  4. S. Sakata, et al., “A Fully-Integrated GaN Doherty Power Amplifier Module with a Compact Frequency-Dependent Compensation Circuit for 5G massive MIMO Base Stations,” IMS 2020
  5. Daehyun Kang, et al., “Design of Bandwidth-Enhanced Doherty Power Amplifiers for Handset Applications,” TMTT 2011
  6. Seunghoon Jee, et al., “A Highly Linear Dual-band Doherty Power Amplifier for Femto-cell Base Stations,” IMS 2015
  7. Yunsik Park, et al., “GaN HEMT MMIC Doherty Power Amplifier With High Gain and High PAE,” MWCL 2015
  8. Jangheon Kim, et al., “GaN-on-SiC Integrated Power Amplifier for 5G Multi-User Massive MIMO Application,” EuMW 2020.