Microwave Journal
www.microwavejournal.com/articles/35439-a-dive-into-integrated-pa-topologies-for-5g-mmimo

A Dive Into Integrated PA Topologies for 5G mMIMO

March 25, 2021

Abstract

The race towards hitting 5G speed, capacity, and availability requirements has come with it a number of nascent foundational technologies. At the forefront of these innovations is massive Multiple-Input Multiple-Output (mMIMO), or the outfitting of a base station with hundreds to thousands of antenna elements, each with its own respective transmit/receive signal chain, to maximize spectral efficiency.

The realization of mMIMO requires a high degree of integration with all components in the transceiver, including the power amplifier (PA). This article discusses the various 5G trends and challenges of mMIMO with a dive into the varying integration topologies for the commonly used Doherty Power Amplifier (DPA). Finally, an introduction to Wolfspeed fully integrated PAs is made by showing good RF performance over wide bandwidths.

5G Infrastructure Trends

Changes in xHaul
In the past, older iterations of 4G base stations (eNodeB) would involve antennas connected to remote radio heads (RRHs) at the top of a cell tower for PHY layer processing that was attached to the baseband unit (BBU) for more complex signal processing. On the network level, multiple RRHs could be served by a pool of BBUs at a far-edge location via the CPRI protocol over a fiber optic link. This centralized RAN topology (C-RAN) has shifted towards a disaggregated network architecture to better fit the varying traffic, throughput, and latency demands of a location. Instead, the 5G architecture involves a function split between the Centralized Unit (CU) and a series of Distributed Units (DU), with the additional potential split of a Radio Unit (RU). In this split, the DU handles low-latency, real-time traffic, while the CU handles non-real-time protocols. This allows for a higher throughput and lower latency communications with a lower layer split (Intra-PHY split). It is known that this split is required in order to support some advanced radio techniques such as Carrier Aggregation (CA) and Coordinated Multipoint (CoMP). For this reason, the enhanced CPRI (eCPRI) protocol was released to better support this functional decomposition.
 
PA Design Challenges with Advanced Radio Techniques
Power Amplifier (PA) design has been increasingly difficult with modern cellular systems ― the OFDM modulation scheme has a high peak-to-average power ratio (PAPR) of around 8-10 dB. This, in turn, requires the amplifier to stay at backoff, well within the linear region to meet adjacent channel power ratio (ACPR) or adjacent channel leakage ratio (ACLR) requirements. The issue with this is when the PA must function within its linear region and away from saturation (its non-linear region), it does not function nearly as efficiently. The use of CA involves the aggregation of available contiguous or non-contiguous blocks of spectrum to increase the throughput and latency of wireless communications in what is typically a populated spectrum (sub-6 GHz). This requires the amplifier to be at additional backoff to avoid the interference of two non-contiguous carriers transmitting simultaneously and to meet strict emissions requirements. Additionally, the amplifier must operate within a wide instantaneous bandwidth, creating a much more complex design challenge to meeting ACLR requirements while maintaining a nominal efficiency.
 
Linearization/efficiency enhancing techniques
These problems have led to the increased utilization of linearization and efficiency enhancing techniques. The Doherty amplifier configuration is amongst the most popular efficiency enhancing methodology for relatively high PAE deep into the output backoff region. Linearization enhancing methods includes digital predistortion (DPD) where the PA is able to operate near saturation without causing nonlinearities. This is accomplished by distorting the input in such way that the distortions at the output are minimized to increase linearity without compromising PAE.
 

mMIMO & The Need for Integration

Architectural Challenges of MIMO
MIMO has been leveraged for some time now in either a passive antenna topology or an active antenna system (AAS). The issue with passive antenna structures is the increase in channels (e.g., 4T4R, 8T8R, 16T16R, 32T32R), which is directly correlated to a larger antenna count and leads to an increasingly higher port density at the antenna. This, in turn, leads to an array of installation issues as well as unwanted signal degradation from the increasing presence of potential Passive Intermodulation distortion (PIM) sources (e.g., coaxial connector heads). The complexity of this problem only increases with mMIMO. This is where the AAS architecture provides a more optimal solution with an integrated antenna/radio, the only connections that are required to the system are a fiber and DC link for power and control. This differs from older base station architectures where a multi-port passive MIMO antenna structure would be connected to an RRH to finally be routed to the BBU.
 
mMIMO PA Design Challenges
mMIMO has with it, its own design challenges. Each transceiver chain must be optimized to minimize the inevitable losses, emissions, and non-linearities that will occur. The PAs in this system must then meet linearity requirements while also considering amplifier efficiency, all in a very integrated system package. The typical use of linearity and efficiency enhancing techniques to better meet ACLR requirements without compromising efficiency greatly involves added circuitry which is not typically integrated into the PA package. This is a significant consideration for mMIMO systems as any additional real estate used at the component-level compounds at the system-level with massive number of antennas and respective transmit/receive chains. An integrated PA design with the most commonly leveraged Doherty configuration and DPD linearization technique can be highly beneficial for system engineers in the installation of mMIMO. This can then afford the designer more flexibility in terms of the basic design requirements on power, size, weight, and cost.
 
Benefits of Using GaN
The use of GaN transistors has already permeated the wireless industry for large, macrocell high powered amplifiers (HPA) and is well positioned to overtake the popularized Si-based LDMOS PA that was previously leveraged. This is due to the intrinsic benefits this substrate has for power applications ― the wide bandgap, combined with its high breakdown electric field, power density allow for the handling of large powers all while exhibiting a sufficient electron mobility and saturation velocity to operate at high frequencies. Ultimately this increases the device's reliability, as the amplifier is able to withstand higher junction temperatures for longer periods of time. GaN transistors are capable of this all within a smaller package and at higher frequencies (DC-40 GHz) as manufacturing techniques advance with large wafer diameters and increasingly smaller gate-lengths (e.g., 0.25μm, 0.15μm) fabrication processes. GaN HEMT technology, in particular, has the capability of achieving a higher efficiency at high frequencies, over a wide bandwidth.
 

Discrete vs Integrated Doherty Power Amplifiers

As mMIMO calls for an increase in integration, smaller form factors are demanded with a high level of linearity and efficiency over a wide bandwidth. Integrating the popularized Doherty PA configuration to enhance efficiency would minimize the 5G New Radio (NR) size and weight and ultimately yield large space savings on the macro-scale in mMIMO installations (See Figure 1). The benefits of small form factor and ease-off-integration come with a number of design considerations though ― chief among them, the operating frequency and operating bandwidth of integrated PAs are fixed. Still, this design constraint can be relaxed by minimizing the bandwidth limitation of the quarter-wave transformer, phase compensation, and the offset lines found in the Doherty configuration.

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Figure 1: Discrete (top) versus integrated (bottom) transistor configurations. Maximal bandwidth can be achieved in the integrated example by minimizing the bandwidth limitations of the quarter-wave transformer, phase compensation, and offset lines.  Image Link
 

The discrete transistor topology (Figure 1a) has the inherent advantages of increased flexibility as it can be tuned to different operating frequencies. As such, its performance can be better optimized. However, additional input/output matching and combining circuits are required leading to a relatively large form factor, an increase in parts, and an additional layer of complexity towards system integration.

GaN on SiC for Integrated Doherty PA Configurations
It is beneficial to leverage GaN-on-SiC for Doherty PA amplifiers due to its high frequency operation (>3 GHz), broadband capabilities with a wide instantaneous bandwidth, high power density, and high efficiency. Since SiC has a very high thermal conductivity of 3.7 W/cm-K than that of GaN at 1.3 W/cm-K or Si at 1.6 W/cm-K, these devices can achieve higher power densities more reliably, leading to a relatively larger load impedance than GaN-on-Si devices. This yields to more compact matching circuits, wideband circuit design, and a lower CDS, qualities that ultimately lend itself towards higher terminal impedance and broader band, high frequency operation. Moreover, a higher efficiency can be achieved by employing harmonic impedance tuning ― a method that changes the load impedances at the 2nd and 3rd harmonics to optimize the Power Added Efficiency (PAE) of the amplifier.
 

Understanding the Varying Integrated Transistor Topologies: An Analysis

There are several potential compact Doherty combining circuits that can be leveraged to achieve an integrated PA. This includes the following (Figure 2):

  • Lumped CLC quarter-wave topology [1]
  • Quasi-lumped quarter-wave topology [2]
  • Lumped LCL quarter-wave topology [3]
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Figure 2: Compact Doherty combining circuits for integrated PA in mMIMO applications [1]-[3].  Image Link
 

Lumped CLC Quarter-Wave Topology

As stated earlier, the bandwidth limiting factors in Doherty PAs are the quarter-wavelength transformer, phase compensation network, and the offset line. The conventional DPA includes the offset line after the quarter-wave transformer in order to compensate for the output capacitance of the transistors and to maintain ideal output load impedance values of both amplifiers. This, however, degrades the effective bandwidth of the system as it has a narrower bandwidth than the quarter-wavelength transformer.

In one iteration of the lumped CLC quarter-wave topology, the output capacitor of the carrier amplifier is merged into the CLC quarter-wave structure while the output capacitor of the peaking amplifier is resonated out with an RF choke inductor. Figure 3 shows the input circuit (3a), output combining circuit (3b), as well as the final schematic representation of the lumped CLC broadband DPA (3c). The use of the quarter-wavelength transformer and the differently biased transistors leads to a need for a phase compensation circuit at the input of a typical DPA. In this topology, the phase compensation network is merged into an input matching circuit [1].

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Figure 3: Schematic representation of the input circuit (a), output circuit (b), and entire circuit (c) for an integrated DPA with a lumped CLC quarter-wave topology [1]Image Link
 
Input Matching Circuit/Phase Compensation Network
The DPA requires a class-C biased peaking amplifier that turns off in low power regions with a class-AB biased carrier amplifier for linearity in the high-power region. However, the gain of the class-C bias grows as the input power increases and because of the turn-on process of the transistor, the input capacitance increases as well, leading to a lower load impedance for the peaking amplifier. Because of this variance in the input impedance with input power level, there is a variance in the division of power between the peaking and carrier amplifiers, ultimately weakening the DPA’s broadband performance. Typically, an additional phase compensation circuit is placed at the input of the DPA to eliminate the phase difference caused by the differently-biased transistors and the addition of the quarter-wavelength transformer. Broadband input matching circuits are employed to enable a consistent division of power and input matching across the bandwidth. However, both these additions take up real-estate while the addition of the phase compensation network generally limits the bandwidth of the DPA. 

It is desirable for more power to be driven to the carrier amplifier at low powers to prevent the peaking amplifier from turning on early ― an event that damages efficiency as the peaking amplifier is drawing more DC current. At high powers, it is also preferable to provide more power to the peaking amplifier in order to ensure proper load modulation and optimal linearity from IMD cancellation. A Wilkinson power divider can accomplish this load modulation by ensuring the input impedance amplifier is mismatched while the input impedance of the peaking amplifier is matched to port impedance at the maximum output power. This way, maximal power is driven to the peaking path at high powers and the effective bandwidth of the DPA is expanded. This topology includes a two-section high-pass filter (HPF) to both compensate for phase and match the input impedance with the addition of the Wilkinson divider to drive a more dynamic load modulation to maximize efficiency and linearity of the system [1][5].



Output Matching Circuits
For the output matching circuit, the ZLoad impedance is increased to reduce the impedance transformation ratio (ITR). A low ITR has a low Q characteristic, a parameter that is inversely proportional to the BW. By ensuring the Q is the same in the output matching circuit for the carrier, peaking amplifier and quarter-wave transformer, the bandwidth is widened (Figure 4).  In this topology, the output capacitance of both the carrier and peaking amplifiers are merged into their output matching circuits. However, this slightly altered topology requires the need for an additional offset line in the output path of the peaking amplifier.
 
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Figure 4: Different Doherty output networks to delivery 8 ohm at Zopt,c and Zopt,p at a center frequency of 1.85 GHz. The network with an unmated Q (left) requires the use of a quarter-wave transformer with a high ITR, narrowing the bandwidth. The matched Q network (right) expands bandwidth with the addition of an offset line [5]Image Link
 

Another output matching circuit lumped CLC quarter-wave topology aims to remove the conventionally leveraged offset line in the peaking amplifier in order to meet the size constraints for mMIMO applications. Typically, DPAs will include a quarter-wavelength offset line in the carrier amplifier and half-wavelength offset line in the peaking amplifier after the output matching networks for proper load modulation and wideband performance. This replacement is accomplished by instead using a series inductor (Lp1), a shunt inductor (Lp2), and a series capacitor (Cp1) after the peaking amplifier (Figure 5). This way, both the frequency dependent compensation functions that the offset lines provide and the output matching functions can be combined into a more simplified, space-constrained circuit. In this circuit, the impedance at power backoff e2 has a similar frequency characteristic to that of a half-wavelength line that acts as an open stub at the center frequency, is inductive at lower frequencies, and capacitive at high frequencies. Moreover, the impedance of the peaking amplifier at saturation e3 can be transformed into any real impedance lower than the optimal impedance of the peaking amplifier e5

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Figure 5: Simulated results (5a) of the impedance looking into the peaking amplifier from the power combinating node at saturation e6 and backoff e7 at different impedance transformation ratios e8 Full schematic diagram (5b) of alternative DPA [4]Image Link
 

In implementing this topology, the bonding wires connecting the peaking FET and the circuit are included in the value of Lp1 while series bonding wires from the carrier FET is included in the output matching network with Lc1, Lc2 while the offset line is formed by the transmission line TLc1 (Figure 5b). This leads to a 10mm by 6mm package (after molding) that is implemented on a multilayer epoxy substrate. Final drain efficiencies stand at 53.7% and PAE at 44.8%, both at 8 dB backoff, while the peak output power is 45.3 dBm, and gain is 28 dB (at 8 dB backoff).

Lumped LCL Quarter-Wave Topology

Output Network
In a lumped LCL quarter-wave topology (Figure 6 (left)), the output capacitance of both amplifiers is resonated out using a shunt inductor. The impedance of the peaking amplifier is inherently high because of this resonance, eliminating the need for an additional offset line. And, instead of using a quarter-wave transmission line, a high-pass LCL circuit is used to perform the same function. This, however, can be simplified by merging the shunt inductors with its adjacent shunt components (Figure 6 (right)). And, because of the large load impedance of the GaN HEMT, the output load impedance can more readily achieve e9
 
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Figure 6: A ℼ-type low-pass and high-pass circuit (left) is used to replace the quarter-wave transmission line in conventional DPAs, saving on space. This can be further optimized by merging in shunt inductive components (Lp and LT) into a singular inductor (L’T) (right)[3]Image Link
 
Input Network: 2nd Harmonic Control Circuit
Several iterations utilizing a lumped LCL quarter-wave topology for the output circuit attempt to mitigate the need for the DPD circuit and maximize linearity by instead cancelling the IM3s of the carrier and peaking amplifiers at the output combining point [6]. A high efficiency (up to 70%) can be accomplished by matching the harmonics to the optimum impedances. In some versions, second harmonic input control circuits are realized through a parallel LC network that experiences resonance (open circuit) at the fundamental frequency. This LC network and the bond-wire exhibits capacitive impedance at the second harmonic frequency generates a series resonance for a short-circuit at the second harmonic frequency [3]. Achieving this second harmonic impedance around the short point can improve drain efficiency considerably (Figure 7). A tunable capacitor can also be used at the input of the carrier amplifier for multi-band operation. This way, the capacitor can be tuned IM3 performance can be optimized for dual-band capability [7]
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Figure 7: 2nd harmonic control circuit used at the input of a lumped LCL quarter-wave DPA topology. Large drain efficiencies and gain of over e11 and 13.5 dB are achieved respectively at 7.2 dB backoff [6]Image Link
 

In some lumped LCL topologies, both the input and output include harmonic control circuitry to match the harmonics of the output impedance for the carrier and peaking amplifiers with the optimum impedances for drain efficiency [7].

Quasi-lumped Quarter-wave Topology

The quasi-lumped, quarter-wave architecture compensates for the output capacitance of the carrier and peaking amplifiers incorporating it in a transmission line, ultimately forming an impedance inverter. This way, by choosing the right length and characteristic impedance of the artificial transmission line the output capacitances and the bond-ware capacitance can be absorbed. And, rather than be limited by the bandwidth of the conventional half-wavelength transmission line impedance inverter and the bandwidth of the parallel resonator (inductor) that is typically used to eliminate the output capacitances [2]. However, this asymmetrical DPA design can lead to sensitivity issues due to the difference in output capacitances between the carrier and peaking amplifiers.

Wolfspeed GaN on SiC Integrated Power Amplifiers for mMIMO

There are some general conclusions that can be gleaned from the previous topologies aiming for an integrated DPA approach. They are as follows:

  • The need for a relatively large load impedance
  • The need to achieve an adequate load modulation of the carrier amplifier through a 90o phase circuit
  • The need to achieve a high output impedance in the peaking amplifier to minimize the power leakage to the FET while ensuring a phase relationship with the carrier amplifier

With all of these considerations there is a general challenge of integrating the phase compensation network, input matching and output harmonic control circuit together on the input side of the DPA. On the output side, combining the output matching network for proper load modulation as well as replacing the offset lines and quarter-wave transformer with discrete inductors and capacitors for comparable wideband performance is the design challenge.

Wolfspeed integrated DPAs offer two topologies (Figure 8) [8]:

  • A final stage integrated PA (includes only final stage)
  • Fully integrated PA (includes both driver and final stages)
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Figure 8: Final stage integrated PA and fully integrated PA with operation in the S-band and ability to cover 200 MHz and 300MHz IBW 4G LTE and 5 NR signals respectively.  Image Link
 
Final Stage Integrated PA performance with DPD Linearization
With DPD linearization, a five carrier (5C), 20 MHz LTE signal ― 100 MHz instantaneous bandwidth (IBW) ― with 8 dB PAPR at a center frequency (fo) of 3.55 GHz, an ACLR of -55.1 dBc to -56.5 dBc is achieved. This is accomplished as well as an average output power of 39.5 dBm and a high efficiency performance. A ten carrier (10C), 20 MHz LTE signal (200 MHz IBW) at 8 dB PAPR and at a fo of 3.5 GHz, an ACLR of -50.3 dBc to -51.7 dBc is gained (Figure 9).
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Figure 9: ACLR plot for Wolfspeed final stage integrated PA with DPD linearization of 5C, 20 MHz LTE signal with 100 MHz IBW (left) and 10C, 20 MHz LTE signal with 200 MHz IBW (right).  Image Link
 
Fully Integrated PA Performance with DPD Linearization
The fully integrated PA tested with a 10C, 20 MHz LTE signal (200 MHz IBW) and a PAPR of 8 dB at a 3.5 GHz center frequency yields an ACLR of -49.9 dBc to -50.3 dBc. An average output power of 37.5 dBm with a high efficiency as well (Figure 10). In other words, it is possible to accomplish an integrated DPA with the input and output driver stages as well as the input and output DPA stages within a small form factor to better fit the needs of 5G mMIMO. Moreover, with the right design and optimization, this can be done under a wide bandwidth signal with up to 300 MHz IBW.
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Figure 10: ACLR plot for Wolfspeed fully integrated PA with DPD linearization for 10C x 20 MHz LTE signal (200 MHz IBW).  Image Link

Conclusion

The various 5G infrastructure trends have led to tighter design tolerances with advanced radio techniques, higher performance requirements, tighter restrictions, and more integration. There is a general call for a higher degree of modularity, PAs for mMIMO are no exception to this trend, where PAs are expected to achieve both a high linearity and efficiency all within a small form factor. This leads to the need for an integrated DPA where a number of design challenges crop up when both minimizing and combining the input and output circuits of the carrier and peaking amplifiers while achieving broadband performance. The GaN HEMT using the GaN on SiC is a promising candidate for the integrated DPA with several advantages including a wide bandwidth performance and the ability to achieve higher efficiencies than other technologies. Wolfspeed 5G mMIMO GaN on SiC integrated PAs show high linearity and efficiency under wide bandwidth signals ― all within a small form factor.

References
  1. Seunghoon Jee, et al., “GaN MMIC Broadband Doherty Power Amplifier,” APMC 2013
  2. J. H. Qureshi, et al., “A Wide-Band 20W LMOS Doherty Power Amplifier,” IMS 2010
  3. Hwiseob Lee, et al., “Highly Efficient Fully Integrated GaN-HEMT Doherty Power Amplifier Based on Compact Load Network,” TMTT 2017
  4. S. Sakata, et al., “A Fully-Integrated GaN Doherty Power Amplifier Module with a Compact Frequency-Dependent Compensation Circuit for 5G massive MIMO Base Stations,” IMS 2020
  5. Daehyun Kang, et al., “Design of Bandwidth-Enhanced Doherty Power Amplifiers for Handset Applications,” TMTT 2011
  6. Seunghoon Jee, et al., “A Highly Linear Dual-band Doherty Power Amplifier for Femto-cell Base Stations,” IMS 2015
  7. Yunsik Park, et al., “GaN HEMT MMIC Doherty Power Amplifier With High Gain and High PAE,” MWCL 2015
  8. Jangheon Kim, et al., “GaN-on-SiC Integrated Power Amplifier for 5G Multi-User Massive MIMO Application,” EuMW 2020.