NI (formerly AWR Corporation) announces that NI AWR Design Environment™ will be on display within the Academic Forum, 5G/RF Pavilion and two technical sessions - High-Efficiency PAs for High PAR Signals Using an NI-Based Platform and Improving the Semiconductor Design-to-Test Flow Panel - during NIWeek 2015, August 3-5 in Austin, Texas. Details include:

Academic Forum – Aug. 3, Austin Convention Center (ACC) Ballroom G

  • Poster presentation from IMS2015 Student Design Competition Winners
  • Software-Defined Radio – University of Erlangen, Germany
  • Software-Defined Radio - Istanbul Technical University, Turkey
  • High-Efficiency Power Amplifier – University of Erlangen, Germany

5G/RF Pavilion – Aug. 4-5, ACC Halls 2-3

  • Bits to Beams: Evaluation of 5G GFDM Modulation
  • Base Station/Femtocell PA Design with 802.11ac/5G GFDM Modulation Signals
  • NI AWR Design Environment: Systems to Circuits to Electromagnetics 

High-Efficiency PAs for High PAR Signals – Aug. 4, 3:30p.m., ACC Ballroom F

Speaker: Dr. Zoya Popovic, UC Boulder

Communication and radar signals have increased peak-to-average power ratios and bandwidths for efficient spectrum use, which implies reduced transmitter average efficiency. Doherty, supply-modulated (ET), and outphasing transmitters offer possible efficiency improvements. At this session, learn about various microwave monolithic integrated circuit (MMIC) power amplifier (PA) designs with 3 W to 10 W output power and peak power-added efficiency greater than 60 percent at X-band using the Qorvo 150 nm gallium nitride (GaN) process. Discover how outphasing and Doherty PAs exhibit load modulation and examine the internal measurements of load modulation in several X-band PAs.

Improving the Semiconductor Design-to-Test Flow Panel– Aug. 5, 10:30a.m., Hilton #408

Panel: Qualcomm, Texas Instruments, Cadence, OptimalPlus, Extreme-EDA and NI

While the semiconductor development process is fairly mature, significant gaps still exist in the typical design flow. Inefficiencies exist between the early design engineering phase, lab characterization, and volume production testing. Siloed flows, duplication of effort, and lack of IP re-use is causing schedule delays and higher costs. In this session, experts in chip design, verification, and test will present their views on the challenges and potential solutions for improving the overall semiconductor development process.

 For complete details for these sessions, visit: