Multi-output clock buffer and divider delivers low jitter to optimize noise performance

Analog Devices Inc. introduced a clock buffer and divider IC (integrated circuit) that combines high-speed, extremely low jitter (41 fs across the 12-kHz to 20-MHz band) and selectable division capability. The 1.65 GHz AD9508 clock buffer is designed for communications, instrumentation, defense and aerospace equipment that require ultra-high-speed data conversion with optimum SNR (signal-to-noise ratio) performance. The device has four dedicated output dividers with bus-programmable division (integers up to 1024) and phase delay, and automatic synchronization. The dividers also have pin-strapping capability for hardwired programming at system power-up. The AD9508 supports up to four differential, or eight single-ended outputs and three logic levels: LVDS (1.65 GHz), HSTL (1.65 GHz), and CMOS (250 MHz).

• View product page, download data sheet and order samples: http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/ad9508/products/product.html
• Learn more about ADI’s clock generation and distribution technology: http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/products/index.html
• View discussions on clocking and timing on EngineerZone™, an online technical support community: http://ez.analog.com/community/clock_and_timing

AD9508 1.65 GHz Clock Buffer and Divider Key Features

• RMS jitter in HSTL output mode:
  • 41 fs @ 622.08 MHz (12 kHz to 20 MHz)
  • 72 fs @ 622.08 MHZ (20 kHz to 80 MHz)
• Dividers are pin-strappable for division factors of 1,2,4,8, or 16
• Outputs: 4 LVDS or HSTL; 8 single-ended CMOS
• Output-to-output skew: <48 ps (LVDS)
• Supply voltage: 2.5 V/3.3 V

Availability, Pricing and Complementary Components

 The AD9508 Clock buffer/divider complements ADI’s clock generator and high-speed data converter portfolio.