- Buyers Guide
Semiconductors / Integrated Circuits
NXP Semiconductors and Audi have signed a strategic partnership for innovation that focuses on innovation speed and time to market in eight selected automotive electronics application segments.
STMicroelectronics, Soitec (Euronext) and Circuits Multi Projets®(CMP) announced that ST’s CMOS 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses innovative silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.
Identive Group Inc. and NXP Semiconductors N.V. are providing innovative near field communication (NFC) payment tags to Yeldi Softcom Pvt Ltd to support the launch of its ‘ara eTap’ cashless payment application in India.
Infineon Technologies AG has introduced its first single-chip radar solutions for applications in industrial and commercial sensing, based on a SiGe process technology and operating in the 24 GHz ISM band.
STMicroelectronics has launched the 2012 iNEMO Design Contest. The contest invites final-year engineering students from the National University of Singapore and the Nanyang Technological University (NTU) to develop innovative applications using ST’s iNEMO® smart multi-sensor technology.
UK, multi-band, multi-standard transceiver chip firm, Lime Microsystems, has announced a partnership agreement with the strategic investment firm In-Q-Tel, an independent, non-profit organisation that identifies innovative technology solutions to support the missions of the US Intelligence Community.
Infineon Technologies has introduced its first power switching devices designed specifically for use in space and avionics applications. The new Radiation Hardened (RH) PowerMOS devices of the BUY25CSXX family are claimed to offer best-in-class performance to support design of energy-efficient power conditioning and power supply systems for space use.
Cadence Design Systems, Inc. and Samsung Electronics have collaborated to deliver a 20 nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration brings new process advances for mobile consumer electronics, enabling design at 20 nm and future process nodes.