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Cadence Design Systems Inc. announced that Fairchild Semiconductor has named Cadence as its primary EDA partner following the signing of a multi-year agreement for key Cadence® mixed-signal technology. Fairchild selected Cadence for its proven ability to provide an interoperable, mixed-signal design and verification solution using Cadence Virtuoso®, Encounter®, Incisive® and Allegro® technologies. A key technology for Fairchild is the Virtuoso Accelerated Parallel Simulator combined with Virtuoso AMS Designer, both part of the Virtuoso Multi-Mode Simulation suite. These technologies accelerate full-chip verification, leading to higher quality products and faster time to market.
"We selected Cadence because of its strong product portfolio, superior technology innovation, dedication to product quality and outstanding customer care," said Benny Chang, Vice President of Analog Technology at Fairchild. "Cadence is the leader in mixed-signal design and verification, and transitioning to a complete Cadence mixed-signal flow permits us to enhance our design productivity."
"Today's imaginative designs are tomorrow's innovative green technology," said Tom Beckley, Corporate Vice President of Custom IC R&D at Cadence. "It's becoming ever-more common that the most innovative companies such as Fairchild are utilizing mixed-signal design and verification technology to reduce energy consumption while still delivering high-quality components. We are very excited to work with Fairchild as its engineers leverage Cadence technology to create some of the most advanced mixed-signal chips on the market."
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