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155 GHz MMIC LNA's with 12dB Gain Fabricated Using a High Yield InP HEMT MMIC Process
A D-band InGaAs/InAlAs/InP high electron mobility transistor (InP HEMT) MMIC low noise amplifier (LNA) developed using a high performance 0.1 µm passivated InP HEMT MMIC process
155 GHz MMIC LNAs with 12 dB Gain Fabricated Using a High Yield InP HEMT MMIC Process
A highly robust, high performance 0.1 mm passivated InGaAs/InAlAs/InP high electron mobility transistor (InP HEMT) MMIC process with frequency capability to 200 GHz and beyond has been developed. This process has demonstrated consistent wafer-to-wafer performance, as well as remarkable uniformity with a wafer average peak transconductance (Gmp) of 1100 mS/mm ±44 mS for more than 1000 sites tested over a two-inch (dia) wafer. A D-band InP HEMT MMIC low noise amplifier (LNA) using this process, which has demonstrated 12 dB gain at 155 GHz, is described. This performance represents the highest frequency solid-state amplifier reported to date.
R. Lai, H. Wang, Y.C. Chen,
T. Block, P.H. Liu, D.C. Streit,
D. Tran, M. Barsky and W. Jones
TRW Electronic Space & Technology Division
Redondo Beach, CA
P. Siegel and T. Gaier
JPL Microwave, LIDAR,
Interferometer Technology Section
©1997 IEEE. Reprinted with permission from Conference Proceedings, 1997 International Conference on Indium Phosphide and Related Materials, May 1997, pp. 241–244.
High performance mm-wave (MMW) LNAs are an important component for advanced communication links, smart munitions, passive imaging and radiometric applications. InP HEMTs have demonstrated the highest extrapolated cutoff frequency and maximum oscillation frequency1–3 of any three-terminal device, making them the future technology of choice for high performance MMW LNAs. However, to date, little data have been reported on actual InP HEMT MMIC amplifiers operating above 100 GHz. Previously, the first and only two-stage 120 and 140 GHz InP HEMT MMIC LNAs that demonstrated 12 and 9 dB gain, respectively, were reported.4,5 Also, the only hybrid one-stage 140 GHz InP HEMT LNA with 7.7 dB gain was described.6 This article presents the first successful three-stage 155 GHz MMIC LNA, which yields 12.5 dB gain from 153 to 155 GHz. This demonstration signifies that the extrapolations on InP HEMT device performance to these frequency levels are valid and that MMIC LNAs designed based on InP HEMT devices should provide useful gain up to 220 GHz. Furthermore, the 0.1 mm InP HEMT MMIC process used to build this chip has attained a high level of maturity with consistent wafer-to-wafer performance and good uniformity over a wafer, making the process suitable for higher levels of production volumes.
The InP HEMT MMIC process7 was developed based on a space-qualified GaAs HEMT MMIC process8,9 to take advantage of knowledge from GaAs HEMT MMIC production development with 70 percent process commonality. The objective for the layer structure design and process flow was to develop the highest performance device possible that would be manufacturable for MMIC applications. The wafers were grown by molecular beam epitaxy (MBE) on two-inch InP semi-insulating substrates. The base line 0.1 mm InP HEMT structure is shown in Figure 1 . The channel is a 150 Å pseudomorphic 65 percent indium composition InGaAs layer, which provides superior transport properties and high electron sheet densities. Typical room temperature Hall mobility of 10,500 to 11,000 cm2/V-sec and Hall sheet carrier concentration of 3.5E12/cm2 are measured on undoped cap layer calibration samples. The devices are isolated using a combination wet-etch/boron implantation process, which provides better than 10 MW/sq resistance. Source and drain ohmic contacts with Ni/Au-Ge/Ag/Au ohmic contacts alloyed at 400°C using rapid thermal annealing provide a low ohmic contact resistance of 0.06 W-mm and source resistance of 0.2 W-mm. 0.1 mm gate stripes are fabricated with a bilayer polymethylmetharylate (PMMA)/ PMMA-methacrylic acid resist profile for metal liftoff and are offset 0.6 mm from the source pad. Prior to metallization, the devices are gate recessed etched to a predetermined current level. The target device pinchoff voltage is –0.25 V with the voltage at a peak transconductance (Vgp) of +0.1 V. A typical device transconductance of 1000 mS/mm is attained using the 65 percent indium composition InGaAs channel with a cutoff frequency of 200 GHz. Device reverse breakdown voltage defined at 0.2 and 1 mA/mm reverse gate leakage current is 1.5 and 2.5 V, respectively. The devices are passivated with 750 Å silicon nitride deposited using plasma-enhanced chemical vapor deposition. For the MMIC process, precision NiCr resistors with a target resistance of 100 W/sq and silicon nitride metal-insulator-metal (MIM) capacitors with a target sheet capacitance of 300 pF/mm2 are formed. After frontside processing, the wafers are lapped and polished to a thickness of 75 mm (three mil). Ground via holes are then wet-chemical etched and 3.5 mm gold is plated on the backside of the wafers to complete the MMIC processing.
0.1 mm pseudomorphic 65 percent InGaAs channel devices have been used for the demonstrated 155 GHz MMIC. For each wafer fabricated, DC characteristics are measured on up to 20 test devices (two-finger, 80 mm total gate width). Figure 2 shows the wafer average peak transconductance for 24 two-inch InP HEMT wafers constituting five wafer lots fabricated over a five-month period. The wafers on which the 155 GHz MMIC design were fabricated are part of this set of 24 wafers. As shown in Figure 3 , remarkable data were achieved on wafer uniformity over a two-inch InP HEMT discrete device wafer. After completion of frontside lithography on one device wafer lot, DC parameters were measured on over 1000 devices over a two-inch InP HEMT wafer. The parameter histograms were measured at 0.7 V drain bias for Gmp and Vgp for this wafer (0.1 ¥ 20 mm device).
Standard deviations of less than 50 mS/mm for Gmp and less than 40 mV for Vgp were achieved. These data demonstrate the good quality and uniformity of the MBE growth, gate lithography, and gate recess etching and wafer fabrication processes. Outstanding wafer-to-wafer device performance repeatability also has been achieved for the InP HEMT process. The wafer average Gmp at 1 V drain bias exhibits 1000 mS/mm (avg) with a standard deviation of only 60 mS/mm. Wafer average Vgp at 1 V drain bias was +0.14 V (avg) with a standard deviation of 50 mV.
155 GHz LNA Results
A family of 35 to 160 GHz MMIC LNAs were developed including a first-iteration 155 GHz LNA design. The three-stage 155 GHz LNA is shown in Figure 4 . The 155 GHz amplifier is a three-stage, single-ended design with a four-finger 30 mm device in each stage. The chip was tested in a G-band (140 to 220 GHz) test fixture with microstrip-to-waveguide E-plane probe transitions fabricated on three-mil quartz.The measured insertion loss for back-to-back transitions was 2.5 dB with a return loss of better than 15 dB from 152 to 168 GHz. Figure 5 shows the gain and input/output return loss for the amplifier from 148 to 158 GHz at Vd = 1 V and Id = 35 mA.
The amplifier exhibits a peak gain of 12.5 dB from 153 to 155 GHz, corrected for the transition losses, and demonstrates greater than 10 dB gain from 151 to 156 GHz with input and output return losses of better than 5 dB and better than 10 dB, respectively. In addition, the DC power consumption of this chip was only 35 mW (Vd = 1.4 V and Id = 25 mA). With Vd = 1 V and Id = 25 mA bias conditions, the peak gain was reduced by 2 dB to 10.5 dB at 153 GHz.
One of the significant results of this MMIC LNA demonstration is that the small-signal InP HEMT device model is verified to 155 GHz and the extrapolated fT and Fmax values for the InP HEMT devices are validated. Figure 6 shows the frequency dependence of gain per stage for InP HEMT MMIC amplifiers operating from 94 to 155 GHz and the calculated maximum available gain from the small-signal InP HEMT device model. The gain per stage is degraded compared to the maximum available gain (MAG) of the InP HEMT due to parasitic inductance from the wet-etch vial hole and losses in the transmission lines and matching networks. Future work to extend the frequency operation to 220 GHz and beyond and to increase gain/stage for LNAs operating at these high frequencies will focus on improving device transconductance, reducing device capacitances, developing smaller inductance via holes and reducing transmission line loss.
The development of a three-stage MMIC InP HEMT LNA operating at 155 GHz with 12.5 dB gain has been described. To the best of the authors' knowledge, this amplifier is the highest frequency three-terminal amplifier demonstrated to date. Based on the results obtained, it is projected that MMIC LNAs operating at 220 GHz and beyond with usable gain will be achievable in the near future with InP HEMT technology.
The authors would like to thank Dick Myers, Halick Parker, Sam Esparza, Yon-Lin Kok and Bill Brunner for device testing and 155 GHz fixture and transition development; and Leniza Go, Rosie Dia, Annika Freudenthal and Nam Nguyen for wafer fabrication. Ed Rezek, Barry Allen and Charles Lawrence are also acknowledged for their advice and guidance. In addition, special thanks are extended to the members of the RF Product Center for their contributions. The results published in this article are supported by TRW internal research and development. Limited amounts of data were taken from JPL contract #960343 with permission. n
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GaAs HEMT Production Process for High Performance V-band Power MMICs," GaAs IC Symposium Digest, San Diego, CA, 1995.
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