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In the past, the cellular base station industry has primarily used 28 V LDMOS for high power amplifier transistors. The recent advance in multicarrier amplifiers implies that cellular signals are wider in nature. This has simultaneously driven the need for higher amplifier power to be generated. At the same time, the volumes requested by operators worldwide have exploded, due to the need for higher data rates and ubiquitous coverage. This is putting a lot of price pressure on the market.
Going forward, 48 V LDMOS is the natural answer to the three above requirements of larger signal bandwidth (35 MHz at 900 MHz and 75 MHz at 1.8 GHz), higher power target and lower price. Indeed, the switch from 28 to 48 V LDMOS allows for unmatched devices that can achieve higher signal bandwidth. The higher voltage operation also means doubling the power output inside the same package, allowing a drastic reduction in the number of output devices to be used. This, in turn, warrants a smaller overall footprint for the mechanics and the circuit. Altogether, the ability to double the power inside the same package warrants a lower cost solution to customers. Yet another advantage of 48 V LDMOS is the high gain associated with the technology (19 dB Doherty gain versus 16.5 dB for 28 V), which eases the power requirement on the driver devices. This translates into an overall boost in system power added efficiency.
Reported to be the first commercially available 48 V LDMOS transistor, specifically developed for the cellular application, it is a 500 W peak power transistor, housed in a cost effective plastic over-molded package. While this transistor can be used in broadband application, the focus of the design work has been centered around the 925 to 960 MHz GSM bandwidth.
Figure 1 shows a cross sectional diagram of a typical high power n-channel LDMOS FET finger from source to drain (left to right). The essential features that allow this device to operate under high drain supply potentials include the drain extension region or Lightly Doped Drain (LDD), and a thick lightly-doped epitaxial deposited layer on the starting substrate, both of which support high drain terminal potentials. 48 V LDMOS was commercially introduced in 2005, but has predominantly been applied in areas outside of cellular infrastructure, which continues to rely on 28 to 32 V LDMOS as the primary device technology. Fundamentally, the same device structural features can be used to create a 48 V LDMOS device structure suitable for cellular applications.
The key to designing a good LDMOS device for a Doherty application (or any other application) is a system view of the PA, where the design of the MOSFET, the internal and external matching networks and the linearization systems can be combined together to maximize the overall PA performance. From a device perspective, this will drive the optimum balance between the RF characteristics (gain, efficiency, raw linearity) and operational reliability characteristics (hot carrier injection, ruggedness, electro-migration) to offer the PA designer the widest latitude and flexibility to meet the PA performance and bandwidth requirements. A good example of the results of using this system level approach, using 48 V LDMOS, is the ruggedness improvements made for devices for industrial CO2 laser systems. This same system approach, for a Doherty PA system, yields a 48 V LDMOS design optimized to provide similarly impressive performance in 900 MHz cellular applications.
The design of the internal on-die matching structures, in particular for high-power and wide RF bandwidth operation, has been a necessity for 28 V LDMOS FETs. By contrast, 48 V LDMOS FET technology, with higher Rp to deliver power and lower Cds-per watt, provides an opportunity that renders internal output matching structures unnecessary, thus avoiding frequency dispersion associated with such structures, and having the means to achieve higher signal bandwidths at higher powers. The internal input match is still needed in order to raise the input impedance to a user-friendly level, even though Cgs-per watt is lower relative to 28 V technology. The design of a complementing input Integrated Passive Device (IPD) was critical for this device. The IPD structures offer opportunities, to not only optimize the RF characteristics (in particular, gain and phase deviation) over the desired operating bandwidth, but also improve the stability of the part in the application, in particular with the added gain offered with 48 V LDMOS technology.
The Doherty amplifier technique has become a staple in the telecom base station arena. The efficiency enhancement that the Doherty amplifier provides is key to reducing the overall base station’s power dissipation. At the same time, the amplifier needs to be linearized using digital pre-distortion (DPD). The off state impedance of the peaking amplifier becomes a factor as the Cds is increased with the added power and thus it loads the main amplifier and reduces the overall efficiency and operating bandwidth. In this regard, 48 V LDMOS technology bodes well as the Cds-per watt is significantly less than that of the 28 V technology.
Today’s high power Doherty amplifiers are composed of two separate devices, which many times have different characteristics resulting in sub-par performance and undesirable factory yields. With the added power density offered by 48 V LDMOS technology, an in-package Doherty amplifier is a very good solution to address this issue. A dual path package is used for the in-package design, which has both the main and peaking amplifier with the associated IPDs. The FETs for the main and peaking amplifier will come from the same wafer and be from adjacent die, thus ensuring very good matching characteristics between the two. In addition, by housing the design in a plastic over molded package, the design will address both the cost and application footprint (power density in a given area), both of which are industry drivers in today’s telecom base stations.
The measurement results shown are based on the plastic over molded, dual-path, in-package Doherty device, designed in a symmetric Doherty amplifier circuit covering the 920 to 960 MHz band. The Doherty amplifier circuit is tested under a single carrier W-CDMA signal, 10.3 dB PAR at CCDF = 0.01 percent for functional performance (see Figures 2 and 3). It is also tested under a 4C-GMSK 35 MHz to demonstrate the linear DPD capability of the design.
The P3dB capability of the device and the Doherty amplifier is 57 dBm (500 W); at 50 dBm Pout, PAR = 7 dB. Also, the open loop ACP is in the mid 30 dBc range and respectable for correction with a DPD system. At 100 W (50 dBm), the average Pout efficiency is approximately 50 percent across the band with a Doherty gain of approximately 19 dB. Figure 4 shows that the device and corresponding Doherty circuit can be linearized, with a DPD system, to 60 dBc or less under the 4C-GMSK 35 MHz signal.
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