David Vye, MWJ Editor
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David Vye is responsible for Microwave Journal's editorial content, article review and special industry reporting. Prior to joining the Journal, Mr. Vye was a product-marketing manager with Ansoft Corporation, responsible for high frequency circuit/system design tools and technical marketing communications. He previously worked for Raytheon Research Division and Advanced Device Center as a Sr. Design Engineer, responsible for PHEMT, HBT and MESFET characterization and modeling as well as MMIC design and test. David also worked at M/A-COM's Advanced Semiconductor Operations developing automated test systems and active device modeling methods for GaAs FETs. He is a 1984 graduate of the University of Massachusetts at Dartmouth, with a concentration in microwave engineering.

DesignCon Heroes 2013

February 7, 2013

DesignCon 2013, the industry-driven conference and exhibition serving the high-speed digital design industry, certainly lived up to its mantra of providing useful, application-specific information to the engineers who need to be in the know about the latest and greatest products in test, simulation, and high-speed components, materials and technology. Held each year in the epicenter of high-speed digital design, aka Silicon Valley, DesignCon drew an impressive and enthusiastic crowd. In turn, the participating companies delivered exceptional content and the overall event was a great learning and networking opportunity for those in attendance. While this event might seem to lie outside the realm of microwave technology, the gigabit data rates of today’s high speed digital design results in many familiar challenges and solution providers.

As the official host sponsor of DesignCon, Agilent Technologies has a large presence in the technical sessions and throughout the exhibition of high speed digital solution providers. Agilent experts presented in the technical paper sessions with tutorials on "Tips and Advanced Techniques for Characterizing a 28 Gbps Transceiver" and "Comparison and Contrast of State-of-the-Art Time Domain Reflectometry Measurement Instruments”. Both these themes will be repeated next month for a Chinese audience at EDI CON 2013 in Beijing. The Agilent education forums, including a 3 hour workshop on the challenges and solutions in characterizing 10Gb devices and a separate morning session on the challenges of DDR4. Panel discussions with Agilent technical experts included "Understanding Digital Communication Standards: A Look Under the Hood" and "Enabling the Next Generation of Smartphones and Tablets with UFS: An Industry Perspective."

In the exhibition area, Agilent was demonstrating the following high-speed design and test solutions:

  • Use of  the compact M8190A arbitrary waveform generator and enhanced N5990A test automation software to obtain faster HDMI and MHL sink compliance test results
  • Agilent’s N1930B physical layer test system (PLTS) 2013 software.
  • Bit error rate testing for 100 gigabit Ethernet applications from 25 to 32 Gb/s using the N4960A Serial BERT and 86100D Infiniium DCA-X wide-bandwidth oscilloscope mainframe;
  • The new 12-bit Infiniium 9000 H-Series high-definition oscilloscopes, which achieves a noise level as much as three times lower than traditional 8-bit oscilloscopes
  • InfiniiVision 4000 X-Series oscilloscopes, featuring a 1-million waveform/s update rate and a 12.1-in. display with touch-screen technology; and
  • A complete high-speed digital design flow using Agilent’s Advanced Design System with DDR4 and 28G as application examples.

 

Anritsu offered several demonstrations involving their MP1800A BER Tester featuring low intrinsic clock jitter of <350 fs (RMS) and a unique eye contour function that allows engineers to evaluate jitter, ISI, and crosstalk at signals up to 32 Gbit/s, necessary to develop countermeasures to ensure signal integrity. The demonstration showed engineers how to account for signal integrity reduction for transmitter and receiver circuits, ensuring the quality of the output signal and receiver tolerance to validate backplane and high-speed interface performance.The MP1800A offers a modular BERT with a built-in Pulse Pattern Generator (PPG) that supports output of high-quality, low intrinsic jitter signals, as well as a built-in Error Detector (ED) with high input sensitivity of 10 mV. It also supports signal analyses, including bathtub and Q measurements.

The company was also showing of its popular VectorStar platform, with industry-best frequency coverage of 70 kHz to 125 GHz and dynamic range of 108 dB at 65 GHz and 107 dB at 110 GHz, and measurement speed of 55 ms for 201 points, making this high-performance VNA  well suited for broadband and millimeter-wave (mmWave) signal integrity applications.

ANSYS earned DesignCon 2013's DesignVision Award for the Modeling and Simulation Tools category. The award recognized the company’s offering of innovative, high-quality tools that simplify the electronic product design process.  Winning for the second year in a row, this year’s award was presented to ANSYS in recognition of its HFSS for ECAD integration which was recently released in ANSYS version 14.5.
 

AWR demonstrated software products that serve the RF, microwave and high-speed digital design communities. In-booth demos included AWR Connected™ partner solutions for PCB flows, Analyst 3D FEM EM simulation capabilities for chip-board-module design and Microwave Office with HSPICE embedded solution for signal integrity studies. Attendees were also able to view the V10.04 Release of the AWR Design Environment™ (Microwave Office® circuit design, Visual System Simulator™ (VSS) software, AXIEM® and Analyst™ EM software) and a demo of AWR Connected to National Instruments (LabVIEW co-simulation for PA design, characterization and test). AWR’s EM technology expert, Dr. John Dunn, gave a workshop entitled, “Modeling High-Speed Interconnect for the Signal Integrity Engineer: Tips, Tricks, and Trade offs.” In the technical sessions.

 

Cadence showcased their software products for high-speed PCB design and analysis. Allegro and Sigrity together provide a power-aware signal integrity solution for DDR3/DDR4 interface design and provides the first comprehensive PCB design and analysis memory interface solution. In addition, the company wwas demoing multi-gigabit interfaces, such as PCI-Express 3.0, which were being simulated by AMI models with back-channel supportAslo featured were the company’s compliance kits, which allow technologists to quickly determine if a channel is designed to meet the interface specifications.

Mike Santori, business and technology fellow at National Instruments, delivered Wednesday's keynote at DesignCon, tracing the evolution of instrumentation through the evolution in standard commercial off-the-shelf electronic products until test automation was empowered by the personal computers in the 1980’s. Santori discussed NI’s introduction of LabVIEW and the concept of virtual instrumentation, where the computer becomes the test platform, leading to the high-performance test solutions that will be driving high-speed design into the future.

NI also won two “Best in Test” awards from Test & Measurement World for its stand-alone NI CompactDAQ system,  an embedded platform equipped with a built-in dual-core Intel processor that runs measurement tests while logging data directly to a portable system, and the NI PXIe-5644R RF vector signal transceiver,a software-designed instrument that combines a vector signal generator, a vector signal analyzer, and a user-programmable FPGA into a single PXI modular instrument.

Mentor Graphics took advantage of DesignCon 2013 to introduce its HyperLynx® PCB analysis products and capabilities. The HyperLynx Analysis Suite offers a PCB analysis environment that includes solutions for DDRx designs, Multi-Gbps Channel analysis, full-wave 3D electromagnetic modeling, and power distribution design for static and dynamic analyses. Mentor Graphics was also a recipient of a Design Vision award from the show organizers, for its IC design platform.

 

Rohde & Schwarz drew a large crowd to their free technical training sessions covering themes such  as USB 2.0 compliance testing, synchronous time and frequency domain measurements using a digital oscilloscope, phase noise and jitter measurements and true differential s-parameter measurements. The increasing cross-over between SI and RF technologies was apparent in the products that R&S and other “microwave T&M vendors” are displaying to the DesignCon audience.

Teledyne LeCroy presented their test solutions for signal integrity in the technical sessions and exhibition space with high-performance test solutions targeting signal integrity engineers and designers. The company offered six papers (below) on topics such as understanding random jitter and debugging SI problems using the company’s SDAIII CompleteLinQ

  • Dramatic Noise Reduction using Guard Traces with Optimized Shorting Vias
  • A Fast and Inexpensive Method for PCB Trace Characterization in Production Environments
  • PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers
  • Understanding Apparent Increasing Random Jitter with Increasing PRBS Test Pattern Lengths
  • Which one is better? Comparing Options to Describe Frequency Dependent Losses
  • Debugging to Find Root Causes Using SDAIII CompleteLinQ

 

On the exhibition floor, the company featured impressive new products with their 65 GHz LabMaster oscilloscope and a new 12-bit HDO high definition oscilloscope, which won a Design Vision award from the show organizers. The high definition display certainly wowed many engineers with its sharp images of otherwise hard to view high-speed signals. This technology allows the HDOs to capture and display signals of up to 1 GHz with high sample rate and 16 times more resolution than other 8-bit oscilloscopes. The high-sample-rate 12-bit ADCs provide high-resolution sampling at up to 2.5 GSamples/s. The scope consists of high-sample-rate 12-bit ADCs, high signal-to-noise ratio amplifiers and a low-noise system architecture. In addition, high-performance input amplifiers deliver very high signal fidelity with a 55dB signal-to-noise ratio that delivers a pristine signal to the ADC to be digitized. The low-noise signal architecture ensures that nothing interferes with the captured signal. As a result, waveforms are cleaner and crisper and signal details often lost in the noise are clearly visible and easy to distinguish, which will make for improved debug and analysis. Other demonstrations included an end-to-end serial data test solutions for transmitter, receiver and protocol-enabled test; PCI Express and DDR protocol analysis and performing 12-port S-parameter analysis with SPARQ Signal Integrity Network Analyzer.

 

Rogers Corporation displayed several examples of its high-quality PCB materials and were on hand to provide advice and guidance on the best use of their MCL-HE-679G/THETA® and RO4000® LoPro™ circuit materials for high-performance digital and analog circuit designs. The RoHS-compliant MCL-HE-679G/THETA circuit materials boast minimal conductor and dielectric losses in support of superior signal-integrity (SI) performance, with a relative dielectric constant of 3.90 in the z-direction at 1 GHz and low dissipation factor of 0.009 at 1 GHz. These laminates are engineered for high reliability over temperature, with a coefficient of thermal expansion (CTE) of only 50 ppm/°C in the z direction, which is about 30% lower than standard FR-4 circuit materials. Such CTE performance is directly related to improved reliability of PCB plated through holes (PTHs), buried blind viaholes, and stacked viaholes in multilayer structures. MCL-HE-679G/THETA circuit materials feature a high glass transition temperature

Isola was also exhibiting their copper-clad laminates and dielectric prepreg materials with a demo of their high-speed digital performance I-Tera® product, the company’s ultra-low loss resin system. The PCB design used in this demo featured a daughter-card backplane configuration with single-ended transmission lines ranging from 16” to 60” (41 cm to 152 cm) routed on I-Tera. Using signals generated by a BERTScope – PRBS31 pattern operating at date rates up to 12.5 Gb/s, Isola displayed the signal integrity of I-Tera by analyzing its rise/fall times, eye width/height, jitter at eye crossing and other key data points to demonstrate the materials performance at high speed data rates.  

Wireless Telecom Group featured the latest in their series of Jitter generator, the JV9000A. This adjustable Vcc noise generator is designed to emulate broadband white system noise and deterministic tones on the power ground planes. These effects can interfere with normal IC timing behavior of PLL's, MIPI interfaces and the phase noise of crystal oscillators. Commonly referred to as "noise on the Vcc input", it can cause an increase in your system jitter if not properly measured and mediated. Such disturbances can enter the circuits through residual capacities on the chip. Designers and manufacturers of integrated circuits need to ensure their products offer sufficient margin against Vcc noise, making them tolerant against noise at these paths.

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