In two-way radio applications, achieving constant efficiency across a wide power level is an important design criterion to be considered. Constant efficiency in this context refers to efficiency improvement at low power level while maintaining high efficiency at high power level. Switched gain stage and drain supply adjustment methods are discussed. With both methods, an efficiency of 45 percent is achieved at low power (1 W) for a frequency range from 420 to 440 MHz, while maintaining the same efficiency at high power with a LDMOS device amplifier.
A power amplifier (PA) achieves maximum efficiency when operating close to saturation. When the input drive signal is backed off, the output power decreases and eventually the efficiency degrades. In two-way radio applications, two modes of operations are allowed, which are high (5 W) and low power (1 W) levels in the UHF frequency band. Thus, it is important to achieve constant efficiency for the two modes of operation levels. In a PA design, constant efficiency can be achieved at both power levels, with supply or load adjustment or both.
Figure 1 Constant efficiency vs. input power level with saturation point control.
Using SiGe HBTs, Leuzzi, et al.1 have shown an efficiency of 20 to 60 percent for a power range of –10 to 5 dBm with load adjustment. Fowler2 used variable bias and supply voltages for efficiency improvements at low power levels and variable load impedance at higher levels. Buoli, et al.3 have demonstrated efficiency improvements by envelope controlled drain supply adjustment applied to GaAs FETs, which led to a reduced DC consumption of 45 percent. Geller, et al.4 showed, for a 1 W amplifier, an efficiency of 65 percent at saturated power and 55 percent when backed off by 10 dB with drain voltage adjustment. Switched gain stage or stage bypass is accomplished by switching the amplifier between the final stage and driver stage according to peak signal level. Staudinger has demonstrated an improvement of the average efficiency from 2.1 to 9.5 percent over a large dynamic range.5 Patent ideas by Sevic6 and Brozovich7 have described an efficiency improvement by selecting the amplifier stage with a switch bypassing scheme.
This article explains the switched gain stage and drain supply adjustment methods to improve efficiency at low power level (1 W) while maintaining the same efficiency at high power (5 W) with an LDMOS PA device. With both methods, an efficiency of 45 percent at low power is demonstrated, while preserving similar efficiency at high power. Issues for both methods, such as nonlinear behavior of the transconductance of the MOSFET, insertion loss of the RF switch and PA gain stage, are discussed.
PRINCIPLE OPERATION OF CONSTANT EFFICIENCY
Figure 2 Load line variation by drain supply (a) and load impedance (b) adjustment.
To achieve low power consumption and maximum battery lifetime, it is desirable that the power stage of a power amplifier chain (assuming multiple stage design) keeps a constant efficiency across a wide range of power levels.1 The efficiency reaches its maximum in the extended saturation region. Hence, controlling the saturation point can produce constant efficiency across varying power levels. Figure 1 shows the constant efficiency area with different saturated power levels. The load line, together with the device characteristics, determines the operation at a certain power level and the allowed excursions of drain current and voltage and thus output power.3 For maximum efficiency, the RF voltage and drain current must swing towards twice the supply voltage and Imax (defined by the maximum FET current) respectively at the desired output power level. Two approaches have been demonstrated so far, which are the adjustment of the drain supply voltage and the adjustment of the load impedance.1
Looking at the I-V characteristics of the transistor (see Figure 2), both arrangements shift the power level to where the saturation of the amplifier occurs. In the first case, the load line is shifted to the left in the I-V plane. In the second case, the slope of the load line becomes less negative. In both cases, saturation occurs at a lower power level and the efficiency is peaked. A reduction of the RF drive level under fixed bias conditions does not allow the DC component of the drain current to drop proportionally to the RF signal.
Figure 3 Stage bypassing architecture of a two-stage power amplifier.
SWITCH GAIN STAGE DESIGN CONSIDERATIONS
The switch gain stage method uses a switch to bypass the final stage amplifier for low power operation. The final amplifier is shut down, which decreases the overall DC power consumption and the amplifier efficiency is increased. The topology in Figure 3 shows the bypassing method of the final stage amplifier. At low power, the Q1 amplifier amplifies the signal with switches SW1 and SW2 switched to point 1. At high power operation, both amplifiers (Q1 and Q2) operate with switch SW1 and SW2 switched to point 2. The slope of the load line decreases due to the lower power levels of Q1 during the bypass mode. Consequently, the drain current is reduced. At low power level, the entire signal is amplified with Q1 and the RF signal is routed from the first stage to the output (via the bypass path). Vg2 is set to pinch off; hence, Id2 is zero.
At higher power level, both stages of the amplifier operate with constant high efficiency. Basically, two RF switches are needed to bypass Q2 and an additional matching circuitry is required to provide the desired Q1 load line in the bypass mode. Mitsubishi RD01MUS1 and RD07MVS1 power MOSFET devices have been used for the first and second stage, respectively. Both amplifiers are built using LDMOS FET technology. CAD models of the RD01MUS1 and RD07MVS1 were developed and used in the simulations.
Figure 4 RF switches in switched gain stage method.
In the RF switch application, resonance tank and PIN diode circuits are introduced for high power (up to 5 W), as shown in Figure 4. For lower power operation, RF switching networks (SW1) and (SW3) are added to bypass the final stage power amplifier. Good correlation of the RF switching (three-port networks) between simulation and measurement results was obtained. In order to deliver 5 W from the final stage, an optimum inter-stage match between the first and final stages must be carried out in the no-bypass mode. In the bypass mode, an additional matching is necessary to achieve the optimum load impedance for low power. A routing path, using a matched transmission line, is necessary in the bypass mode.
DRAIN SUPPLY ADJUSTMENT DESIGN CONSIDERATIONS
In this method, the drain supply voltage is adjusted according to the required power level. A reduction of the RF drive level under fixed bias conditions does not allow the DC component of the drain current to drop proportionally to the RF signal. If the drain bias is decreased when the RF drive is reduced, the DC component can be reduced substantially. The optimum drain supply voltage VDSopt for any power operation can be expressed as
Vk can be obtained from the IDS–VDS characteristics, either from simulation or from measurement. In addition to the reduction of VDS, a small increase (more positive) of the gate voltage is helpful to increase the average gm.4 Thus, this will increase the gain and PAE. The MOSFET transconductance gm is defined as the change of drain current IDS with respect to the corresponding change of gate voltage VGS8 with VDS constant.
Knowing the ID of an N-channel MOSFET, one can derive the gm in the saturation region as
To increase gm, the channel width W of the transistor can be increased, but this also increases the channel length L and reduces the oxide thickness.8 Equation 3 shows that an increment of VGS helps to boost up gm. Biasing the amplifier in the class AB mode is effective, with respect to the control of the gate biasing, for optimum efficiency (PAE) adjustment. The simulation analysis showed the degradation of gm below VDS = 4.8 V for the RD07MVS1 (LDMOS) device. This is illustrated graphically in Figure 5.
Figure 5 Transconductance gm vs. VDS for the RD07MVS1 device.
The concept of achieving constant efficiency with the proposed methods is validated through on-board measurements. A test board using an FR-4 substrate material was fabricated. The PCB has a dielectric constant of 4.5 and a thickness of 14 mils. For the switched gain stage, RD01MUS1 (first stage) and RD07MVS1 (second stage) are used in the experiment. And for the drain supply adjustment method, only the RD07MVS1 device is used to prove the concept. For each method, two different test boards were fabricated. Optimizations are done for each board at an early stage to meet the power performance. A heat sink is mounted at the bottom of the test board (for the RD07MVS1) for good heat transfer.
Figure 6 Simulated and measured efficiency vs. output power for the two-stage amplifier in the bypass model.
SWITCHED GAIN STAGE RESULTS
The efficiency measurement results across the power level range for bypass and non-bypass modes are shown in Figures 6 and 7, respectively. The insertion loss of the RF switch is 0.29 and 0.58 dB during bypass and non-bypass mode, respectively. An isolation greater than 28 dB is obtained for bypass and non-bypass modes. The measured efficiency is improved by 25 percent at low power (1 W) in the bypass mode. A degradation in efficiency of 7 percent at 5 W is experienced in the non-bypass mode. This is due to the insertion loss (0.58 dB) of the RF switch between the inter-stage matching circuit and the output final stage amplifier in the non-bypass mode. Good correlation is observed between measurement and simulation results.
Figure 7 Simulated and measured efficiency vs. output power for the two-stage amplifier in the non-bypass mode.
Nevertheless, constant efficiency could be achieved for the wide power range from 1 to 5 W. If the first stage power amplifier saturates at higher power, it can produce a constant high efficiency. Experimental results prove that the device gain is important. Possible wideband amplifier devices, with wider dynamic range, may increase the versatility of the proposed technique.
Figure 8 Simulated and measured efficiency vs. output power with drain voltage adjustment.
DRAIN SUPPLY ADJUSTMENT RESULTS
Simulated and measured efficiency versus POUT are shown in Figure 8. The results show a constant efficiency of 45 percent at low (1 W) and high power (5 W). The input RF drive to the power amplifier has to change according to the required output power. The input RF drive to the power amplifier requires a dynamic range of 10 dB. A slight decrease in gain was experienced below 4.8 V, which was already predicted through calculation and simulation due to the gm of the device dropping in this region. Below this point, the gate bias voltage is increased to maintain PAE and gain. The device is operating in class AB. The measurement results showed good correlation with simulation. A summary of the performance of switched gain stage and drain supply adjustment methods is illustrated in Table 1.
Enhancement of efficiency at low power (1 W) operation, while maintaining the same efficiency at high power (5 W) with switched gain stage and drain supply adjustment methods, is demonstrated. Efficiency improvement of 25 percent with bypass mode for low power (1 W) and with degradation of 7 percent at high power (5 W) are achieved. With a lower insertion loss of RF switch, the efficiency at high power will be maintained in the non-bypass mode. An efficiency of 45 percent, across a wide range of power level (1 to 5 W), is achieved with the drain supply adjustment method. The transconductance of the active device is analyzed and a class AB bias scheme is proposed. The gain drop at very low power levels can be compensated by a slight increase in gate source voltage.
1. G. Leuzzi and C. Micheli, “Variable Load Constant Efficiency Power Amplifier for Mobile Communication Applications,” 2003 IEEE European Microwave Conference Digest, pp. 375–378.
2. T. Fowler, “Efficiency Improvement Techniques at Low Power Levels for Linear CDMA and WCDMA Power Amplifiers,” 2002 IEEE RFIC Symposium Proceedings, pp. 41–44.
3. C. Buoli, A. Abbiati and D. Riccardi, “Microwave Power Amplifier with ‘Envelope Controlled’ Drain Power Supply,” 1995 European Microwave Conference Proceedings, pp. 31–35.
4. B.D. Geller, F.T. Assal, R.K. Gupta and P.K. Cline, “A Technique for the Maintenance of FET Power Amplifier Efficiency Under Back Off,” 1989 IEEE MTT-S International Microwave Symposium Digest, pp. 949–952.
5. J. Staudinger, “Applying Switched Gain Stage Concepts to Improve Efficiency and Linearity for Mobile CDMA Power Amplification,” Microwave Journal, Vol. 43, No. 9, September 2000, pp. 153–162.
6. J.F. Sevic and R.J. Camarillo, Efficient Parallel Stage Power Amplifier, US Patent 5,872,481, February 1999.
7. R.S. Brozovich, High Efficiency Multiple Power Level Amplifier Circuit, US Patent 5,661,434, August 1997.
8. D.A. Neamans, Semiconductor Physics and Devices Basic Principle, McGraw-Hill, New York, NY, 2003.