Cadence Design Systems, Inc. announced that it has collaborated with Samsung Foundry to deliver qualified Mixed-Signal OpenAccess-ready process design kit (PDK) technology files that support a range of Samsung process technologies from 28FDS to GAA base 3 nm. The Mixed-Signal OpenAccess-ready PDK allows mutual customers to speed their time to market by ensuring that the qualified Cadence® custom and digital design tools seamlessly interoperate on various Samsung process technologies. The Mixed-Signal OpenAccess-ready PDK improves productivity for mixed-signal designs used in data centers, networking, 5G, mobile, industrial and automotive applications.
The Cadence digital tools included with the Mixed-Signal OpenAccess PDK for Samsung process technologies are the Innovus™ Implementation System, Genus™ Synthesis Solution, Liberate™ Characterization Suite, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ Extraction Solution, Physical Verification System, Tempus™ Timing Signoff Solution, Voltus™-Fi Custom Power Integrity Solution, and Litho Physical Analyzer. The Cadence custom tools included in the PDK are the Virtuoso® ADE Product Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design, Spectre® X Simulator and LDE Electrical Analyzer.
Using the Mixed-Signal OpenAccess-ready PDK with the Virtuoso and Innovus platforms, customers can seamlessly access mixed-signal designs in a common OpenAccess database. This co-design methodology promotes shared responsibilities and collaboration between the analog and digital teams for chip planning, design, implementation, physical verification and signoff, improving overall productivity and increasing design throughput.
The Mixed-Signal OpenAccess-ready PDK enables the use of the flows, which offer:
- Advanced floorplanning and pin optimization: Users can pre-plan sensitive analog parts of the design using constraint-driven placement in the Virtuoso platform, then open the same design in the Innovus system for timing-driven placement of digital blocks. Users can fix pin locations or move them in either tool to optimize routing.
- Powerful block and chip routing capabilities: Users can pre-route sensitive analog nets using custom design tools and finish the rest using a fast timing-driven router with in-design DFM hotspot detection and automated fixing to fulfill the mandatory DFM signoff requirements.
- Improved static timing analysis: The Innovus and Tempus solutions automatically recognize logic cells on the timing path in mixed-signal design and perform timing analysis while ignoring analog circuitry that does not impacting timing.
- Improved EM-IR Analysis: Enables faster electromigration IR drop (EM-IR) analysis for mixed-signal designs through a new hierarchical approach.
“We have qualified the Cadence Mixed-Signal OpenAccess-ready PDKs, and our IP designers are taking advantage of the interoperability of the Virtuoso and Innovus flow for our internal designs,” said Jongwook Kye, vice president, Foundry Design Enablement at Samsung Electronics. “This flow is available to our mutual customers immediately and will allow them to create high-quality designs on our various process technologies. This collaboration signifies further progress in our ongoing innovation with Cadence and ensures our customers continue to have access to the tools needed to improve productivity and speed their design process.”
“In collaboration with Samsung, we’ve developed a Mixed-Signal OpenAccess PDK that enables customers to create mixed-signal designs for emerging applications more effectively,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “With this new PDK, customers can leverage the Cadence digital and custom tools and Samsung’s process technologies to achieve improved power, performance and area and successfully deliver new designs within tight market windows.”
The Cadence digital and custom flow supports the Cadence Intelligent System Design™ strategy, enabling customers to achieve system-on-chip design excellence.