8 to 15 GHz High Spectral Purity PLDROs for LMDS and MVDS Applications

Nexyn Corp.
Sunnyvale, CA

Local multipoint distribution systems (LMDS) and multipoint video distribution systems (MVDS) are paving the way for future telecommunication services by offering expanded channels and enormous data rates. LMDS and MVDS transmitters use mm-wave signals between 27.5 and 31.3 GHz to transmit voice, video and data, and high speed Internet services to line-of-sight homes and offices within a three- to 10-mile-diameter operating cell. Using a conservative quadrature phase-shift keying modulation scheme, roughly 1 Gbps of digital data can be transmitted within 1 GHz of wireless spectrum. LMDS can be used for two-way wireless transmission to provide interactive services without the per home expense encountered on fiber or copper coax lines, thus promising a wireless alternative to fiber and coax.

However, there are technical challenges associated with the opportunities created by LMDS technology. One of those key challenges is developing a low cost 27 GHz up-/downconverter used for receiving and transmitting the 28 GHz signal to and from the hub (a transceiver). An up-/downconverter in the transceiver changes the mm-wave carrier signals to a lower IF that can be manipulated inexpensively. Figure 1 shows a simplified block diagram of such a transceiver. The heart of the up-/downconverter is a frequency-stable LO that operates around 27 GHz. The use of a frequency-stable LO is imperative to the performance of the LMDS for clock recovery and high data rate operation with low bit error rate. Phased-locked oscillators at one-half or one-third the mm-wave frequencies are chosen instead of fundamental mm-wave frequency oscillators for a number of reasons: They are less difficult to design and manufacture, low noise transistors are available for the oscillator circuit and phase locking at a lower frequency is more efficient. In addition, component reliability is higher, overall component and labor costs are much lower and the doubling or tripling multiplier/filter scheme yields good efficiency and minimizes cost. Besides low cost, the frequency-stable LO also requires high spectral purity for the modulation scheme to create high channel capacity. When the LO is multiplied up two or three times, the phase noise is also doubled or tripled. It becomes apparent that the phase noise of the fundamental LO must have ample margin before frequency multiplication.

Dielectric resonator oscillators (DRO) have long earned their reputation as highly temperature stable, very low phase noise and cost-effective microwave sources for telecommunication systems. When DROs are phase locked to a clean, stable crystal reference, their noise performance reaches an unmatched level. The NXPLOS series phase-locked DROs (PLDRO) with ultra-low phase noise have been developed for use in current and future telecommunication systems. This article describes the performance of a 13.2 GHz PLDRO, which is doubled to 26.4 GHz for an LMDS base station application.

The PLDRO Design

The loaded Q of the DRO's dielectric resonator at 13.2 GHz was measured to exceed 1700 within the cavity. To keep cost down, the active device used is a low cost Ku-band packaged GaAs FET. Microwave frequency printed circuit material is used for the oscillator circuit instead of the more conventional chip device and thin-film MIC construction. This PCB construction and the packaged device approach eliminate the stringent environmental requirements for thin-film circuits, thus fulfilling the objective of lower material, equipment and labor costs. It should be noted that the task of accurate circuit simulation and modeling is critical to consistent success and modal elimination. An EM simulation software program was used to check the circuit layout and coupling structure before fabrication. The free-running DRO's impressive phase noise performance at 13.2 GHz is listed in Table 1 , showing the clear advantage of using a high Q dielectric resonator.

Table I
Measured Phase Noise at 13.2 GHz (dBc/Hz)


Free-running DRO

Phase-locked DRO

1 kHz



10 kHz



100 kHz



1 MHz



The free-running DRO has a total temperature stability of +2.5 ppm/°C and can be electronically tuned to 12 MHz (typ) at 12 V using a varactor. In order to improve the close-in phase noise and frequency stability, the DRO is phase locked to a very stable and clean 100 MHz external reference. The output frequency of the DRO is sampled through a coupler and used as the LO to drive the mixer diodes in the sampling phase detector. The 100 MHz reference signal is amplified to drive the step recovery diode in the sampling phase detector to generate higher harmonics. The Schottky mixer diodes (within the sampler) function as a phase detector to compare the harmonic frequencies with the LO frequency (13.2 GHz).

Differences in frequency create the differential error voltages that are fed to an active loop filter. The loop filter generates an output error voltage to the varactor that tunes the DRO frequencies opposite the direction of the frequency error. Zero phase error (phase locked) is reached when multiples of the reference frequency (in this case, the 132nd harmonic of 100 MHz) are equal to the DRO frequency. Within the loop bandwidth, the phase noise of the DRO is reduced by the total gain of the phase-locked loop (PLL) at a rate of -40 dB/decade in close to the carrier to -20 dB/decade near the loop bandwidth. The loop bandwidth is optimized to produce the maximum noise roll off within the loop bandwidth while maintaining loop stability over the entire operating temperature range. The total loop gain is dependent on the phase detector gain, oscillator modulation sensitivity and loop filter gain.

The theoretical lower limit of phase noise within the loop is limited by the multiplied reference oscillator noise plus any noise contributed by the loop amplifier circuit, or the noise floor of the phase detector, whichever is higher. Outside the loop bandwidth, the phase noise of the DRO dominates. The excellent temperature stability characteristics of a DRO keep loop stress to a minimum over temperature changes, making it less likely to break out of lock over a wide temperature change and helping to maintain a high loop gain.

Note from the phase noise data under phase-locked operation that the close-in phase noise is drastically reduced by the PLL within the loop bandwidth (using a loop bandwidth of approximately 200 kHz). Typical phase noise levels at 1 kHz, 10 kHz, 100 kHz and 1 MHz offsets are -105, -115, -121 and -135 dBc/Hz, respectively, as shown in Figure 2 . Such high spectral purity is ideal for applications in LMDS and MVDS base stations and rooftop transceivers as well as for very small aperture terminal, digital radio and RADAR receiver applications.

Table II
Typical Performance of the NXPLOS Phase-locked DRO's

Output Frequencies (GHz)

8 to 15

Output Power (dBm)

+13 (typ)

Power Variation (-10° to 65ºC) (dB)


External Reference Frequency (MHz)


Reference input level (dBm)

+10 (nom)

Harmonics (dBc)

< -25

Spurious (dBc)

< -80 (typ)

Phase Noise
at 1 kHz (dBc/Hz)
at 10 kHz (dBc/Hz)
at 100 kHz (dBc/Hz)
at 1 MHz (dBc/Hz)


Power Supply

+12V at 180mA

Table 2 lists typical specifications of the PLDROs designed to operate from 8 to 15 GHz. Other design features include good immunity to power supply ripple and reduced microphonics commonly found in phase-locked sources when integrated in the system. The NXPLOS series PLDROs are supplied in a 2.25" x 2.25" x 0.65" housing.


When compared to competing higher cost phase-locked permanent magnet YIG oscillators, PLDROs have lower power consumption and good temperature stability. Thus, PLDROs are a sound choice as LOs for both current and future telecommunication systems. For additional NXPLOS phase-locked or free-running DRO product information, visit the company's Web site at www.nexyn.com.

Nexyn Corp.,
Sunnyvale, CA
(408) 732-0793