An MCM BGA Platform for Commercial Systems Applications

This article describes the implementation of ball grid array (BGA) packaging as a low cost platform for use in commercial systems applications. The BGA platform is an efficient technique used for interconnecting semiconductor die to a substrate. The platform distributes RF and DC signals to a circuit grid manageable by the system PCB, thus avoiding the expenses associated with a high density PCB. The BGA comprises a multilayer PCB with semiconductor components, MMICs and application-specific ICs (ASIC), encapsulated with a thermally conductive insulating material. The interconnections between the board and the system are made by eutectic-attached lead tin solder balls. BGAs offer ease of assembly, reduced electrical parasitics and improved thermal management characteristics. The platform combines different and incompatible IC fabrication processes for enhanced performance and functionality. The system designer is only required to incorporate a single component as opposed to several individual packaged die. The circuit selected to evaluate the BGA technique, a DC to 2 GHz, six-bit, 31.5 dB digital attenuator with driver, consists of two GaAs RF MMICs with silicon ASIC TTL drivers. The design methodology for the BGA is presented with performance and cost analyses of the attenuator in a ceramic and plastic platform.

Alan Noll
Lowell, MA

The characteristics of the multichip module (MCM) BGA platform are shown in Figure 1 . The main element of the BGA is the PCB. On the top surface of the platform are the DC and RF circuit traces and component die. Components are attached with epoxy, and connections between the die and traces are made with thermocompression bonds. The top surface, die and bonds are encapsulated with a molding compound, and the bottom of the PCB features the grid trace pattern for the solder balls. Connections between the solder balls and top side traces are made by plated-thru-hole vias. Solder mask is applied to both surfaces to fill the vias partially.

Many device types can be contained within a single package; BGAs allow silicon ASICs, GaAs MMICs and passive components to be integrated within the package outline. The designer can make use of mature, commonly available die without the need for modification prior to manufacturing the BGA. The package has the advantage of providing short electrical paths, thus reducing inductance, capacitance and resistance parasitics. The Joint Electronic Device Engineering Council (JEDEC) has generated specification MO-151, which lists the standard outlines from 7 mm (0.275") square to 50 mm (1.96") square. These outlines are available for the designer to select for the specific application.

BGAs also allow for the reduction of the total number of packages to achieve the same functionality. This component integration lowers the system cost by reducing the size, number of layers and complexity of the system PCB. BGAs can be assembled onto the system PCB using standard surface-mount technology reflow solder processes. The BGAs also can self align onto the system PCB during reflow soldering.

Concerns about repair and replacement are minimized with the development of reliable replacement methodology. Process optimization eliminates the need for bump inspection, and underfill improves the reliability of the BGA attachment by providing stress relief during thermal and mechanical environments. Another advantage of the MCM BGA platform is the reduced time to market offered for a new product without a required custom package design.

The Design
The objective of this project was to develop an MCM BGA platform that would be equivalent to the model AT20-0107, a DC to 2 GHz, 31.5 dB, six-bit digital attenuator with a CMOS TTL driver. This attenuator is used in commercial base station applications as a gain leveling control circuit. The baseline platform is a ceramic lead frame. The device and schematic are shown in Figures 2 and 3 , respectively. The digital attenuator is realized by integrating two GaAs MMIC attenuators with two ASIC TTL drivers, and the attenuator function is achieved by a one-bit, 16 dB attenuator and a five-bit, 15.5 dB attenuator. The ASICs are quad CMOS drivers that translate the TTL control inputs into gate control voltages for the GaAs FET MMICs.

For a low cost BGA design, a laminate is selected for the substrate. The laminate should feature a high glass transition temperature Tg and multilayer construction with a thickness greater than 0.020" for dimensional stability. In addition, the laminate must be panelized to optimize assembly machine time, be gold plated for wire bond and soldering, and contain plated thru holes with solder mask coating.

The material selected for this project was the GETEK laminate, featuring a Tg of +180°C, dielectric constant er of 4.2 and a loss tangent of 0.013. The copper thickness is 0.5 oz for RF trace layers and 1 oz for internal ground layers, and the finish for the external copper is gold plating. The solder mask conforms to IPC-SM840 specifications. A four-layer configuration was selected, as shown in Figure 4 , with the primary and secondary dielectric thickness equal to 12 mil for a total thickness of 31 mil.

The BGA pattern was designed using several design guidelines. The pitch and diameter of the balls are defined in the JEDEC specification MO-151. For this application, a 50 mil pitch and 30 mil diameter were used and current PCB production fabrication minimums were used for other key dimensions. The plated thru holes are 13 mil diameter with a 5 mil angular ring. The DC trace line width and offset are 4 mils minimum and the RF transmission line is coplanar microstrip with a 23 mil line width and 12 mil spacing.

The assembly processes are standard and compatible for high volume automated production manufacturing. Other design features include components that are die attached with silver-filled conductive epoxy, interconnects made by thermocompression bonding of 1 mil diameter gold wire and a molding compound applied using dam and fill encapsulation of the component surface. The solder balls were attached by screening solder paste on the secondary layer and applying 0.030" diameter lead tin solder balls. Figure 5 shows the BGA assembly top layer and the solder ball array pattern of the bottom layer.


The Test Data
The digital attenuator BGA was assembled onto a PCB and electrical testing was performed. A comparison of the test data vs. the baseline specification is listed in Table 1 .

Table I
BGA Test Data


Baseline Specifications

Test Data


DC to 2

0.01 to 2

Insertion Loss (dB)



Return loss (all states) (dB)




0.5± 0.215
± 0.230
± 0.260
± 0.320
± 0.440
± 0.680
± 1.145

0.50 to 0.60
1.05 to 1.10
2.00 to 2.15
3.95 to 4.20
8.00 to 8.30
15.50 to 15.80
31.00 to 31.50

The results reveal that the attenuator manufactured in a BGA platform is equivalent to the ceramic platform. The BGA platform is compared to other platforms used. Table 2 lists the key electrical and mechanical parameters of the MCM BGA platform vs. ceramic and plastic.

Table II
Product Differentiation





Die per package

< 4

6 to 10

1 to 2


< 4

< 8 laminate

< 2

Multilayer circuits












PCB Intergration




Time to Market (weeks)

10 to 12

4 to 6

4 to 6

Total Manufacturing Cost (10,000)


25% Savings

66% Savings

Nonrecurring engineering costs




As noted previously, the BGA platform offers a greater level of die integration, good thermal performance and higher frequency of operation. In addition, the platform utilizes standard manufacturing processes for assembly and insertion into system PCBs. The outline comparison of the six-bit digital attenuator is shown in Figure 6 . Note that the BGA is less than one-half the area of the baseline ceramic package.

An MCM BGA platform that produces a BGA that is equivalent to the model AT20-0107 attenuator has been described. Throughout the project, the basic BGA design concepts were acquired and the characteristics of the MCM BGA platform were compared to similar ceramic and plastic commercial platforms. The MCM BGA platform offers a low cost package technique with high integration capability in the commercial operating frequency bands.

This article is a result of the collaboration of many M/A-COM employees. The author wishes to thank J.P. Lanteri, Dick Anderson, Lucky Hongsmatip, Murat Eron, Jim Stone, Andy Smethurst, Ron Carrick and the MAFET processing lab personnel for their assistance in this project. The model AT20-0107 attenuator is a product of AMP M/A-COM.

1. Dennis Stephenson, "MCP vs. MCM: The Evolution of a Multichip Technology," Advanced Packaging, Vol. 5:2, March/April 1996, pp. 20-23.

2. "J-STD-012, Joint Industry Standard, Implementation of Flip-chip and Chip Scale Technology," Institute for Interconnecting and Packaging Circuits (IPC), Sept. 1996.

Alan Noll received his BSEET from the University of Massachusetts at North Dartmouth in 1976. His experience includes the design of multifunction assemblies containing passive and active MIC components and the re-engineering of products for the insertion of GaAs MMIC and glass technologies. Currently, he is a principal engineer at AMP M/A-COM in the Actives Business Unit, where he is involved in the design of control components for commercial and defense applications.