Sapphicon Semiconductor, a designer and manufacturer of high performance integrated circuits based on silicon-on-sapphire (SoS) process technology, and AWR Corp., a leader in high frequency EDA, introduced process design kits (PDK) for AWR software that support Sapphicon’s advanced SoS processes.

AWR’s Analog Office® RFIC design software is used to develop Sapphicon PDKs because of its ability to provide extremely accurate models. Sapphicon presently offers AWR PDKs for all variants of its 0.25 µm process and is currently working on PDKs covering its 0.5-µm high-frequency RF/mixed-signal complementary metal oxide semiconductor (CMOS) processes.

SoS is an ideal process for high-frequency and mixed-signal devices as its insulating substrate eliminates parasitic capacitance from the circuit, which allows higher frequencies, low power consumption and high Q passives (e.g., inductor QL greater than 40 at 2 GHz) to be achieved. Transistors created using SoS technology also have much lower junction capacitance and thus have fewer nonlinearities at high frequencies than those manufactured with standard CMOS processes.

“A key aim is to develop highly accurate models for transistors and passives such as spiral inductors at frequencies up to 40 GHz,” said Yash Moghe, Sapphicon’s Design Engineering Manager. “Analog Office software enables us to accurately model active devices, passives and interconnects on SoS so that our customers realize first-time-right designs.”

“This partnership extends our reach by providing Analog Office customers with access to a wider variety of process technologies,” said Graeme Ritchie, RFIC Segment Manager at AWR. “Sapphicon’s SoS technology is ideal for RF and mixed-signal CMOS designs.”