IMEC will use SUSS MicroTec's XBC300 production wafer bonder platform to develop 200 and 300 mm permanent metallic interconnect bonding, as well as temporary bonding and debonding solutions for its 3D-stacked interconnect and 3D wafer level packaging technology. This universal platform can support a wide range of materials and processes and allows debonding dies at room temperature, which is an important condition for the integration of memory ICs and CMOS image sensors. The bond cluster also includes a spin coater, a low force bonder and a plasma chamber.
For its 3D IC technology, IMEC uses a process flow where TSVs are realized in a single-damascene process that is performed immediately after front-end and contact processing but prior to processing of the back-end metallization layers. This process enables small via diameters of 1 to 5 µm. After completion of the back-end wiring, silicon is removed from the bottom of the substrate to open the buried TSVs. Subsequently, dies or wafers are stacked and interconnected in a wafer bonding step.
"We are very pleased to co-develop with SUSS MicroTec the processes for permanent and temporary wafer bonding for our 3D technologies," said Eric Beyne, Program Director of IMEC's advanced packaging and interconnect research centre. "In particular, the debonding and handling of very thin wafers ranging from 25 to 50 µm is an especially challenging and critical process. We are convinced that the versatility of the SUSS wafer bonding and debonding tool platform will contribute to bringing 3D integration technology to maturity."