The fundamental impedance Zfundamental is expressed in Equation 19:

where R* denotes the optimized load impedance, ranging from 15.89 to 46.29 Ω, and the coefficient γ is between -1 and 1.

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To satisfy the design requirements of the Class-EFJ PA, the input impedance is within the range of 15.89 to 46.29 Ω using π-type matching networks. The optimized fundamental load impedance falls within the left half of the Smith chart.

Figure 5

Figure 5 Simulated the Z6 (1/Y6) of the coupling structure.

From Equations 6 and 7, the coupling structure can be calculated. Impedance values of the coupling structure, 1/Y6, from 0.6 to 3.3 GHz are 34.24 to 49.37 Ω (see Figure 5). These values are transferred to the input impedance through the π-shaped network; these are also the output impedance values for the Class-EFJ PA.

The PA direct current (DC) drain bias serves as part of the output matching circuit. It replaces Y5 in the π-shaped network. The above design not only minimizes the size of the output matching circuit but also controls the second and third harmonics. This is becausethe λ/4 microwave line ensures a short circuit for the second harmonic and an open circuit for the third harmonic at the device output. This simple compact circuit provides the theoretical foundation for high efficiency and broad bandwidth.

PA DESIGN

To validate the proposed structure, a multi-octave Class-EFJ PA is designed and fabricated using a 10 W CGH40010F GaN HEMT on SiC, mounted to a Rogers 4350B circuit board (εr = 3.66, thickness = 0.762 mm). The device is biased with a drain voltage of 28 V and a gate voltage of –2.7 V. The target band is 2.7 GHz.

To ensure the accuracy of the output matching circuit, the impedance Y5 (see Figure 4) is replaced with the drain bias line in Figure 6 as a key part of the output matching circuit. The packaging parasitic parameters and π-shape network are shown in Figures 6a and 6b, respectively.11

Figure 6

Figure 6 Transistor package model (a) and output matching network (b).

Figure 7

Figure 7 Output impedance at the current plane and the optimal fundamental impedance.

Figure 7 shows the fundamental load impedance presented by the output matching network at the intrinsic device plane, along with the design space for optimal fundamental impedances. The fundamental load impedance of the output matching network falls within the Class-EFJ design space. However, due to the optimization of transmission lines TL5 and TL7, the realized impedance exhibits a slight deviation from the ideal theoretical target.

The proposed structure can also improve efficiency by controlling the harmonics. The bias drain line TL5 and the series microwave line TL7 can control the second and third harmonics, as the sum of the electrical length is 85 degrees, which is approximately equal to a l/4 line. The l/4 microstrip line presents a short circuit at the second harmonic and an open circuit at the third harmonic. The electrical length of TL7, TL1 (or TL2) and the sectorial Stub 4 is about 30 degrees (λ/12), which controls the third harmonic.

The analysis demonstrates that the π-shaped output matching network with a coupling structure can effectively control fundamental and harmonic load conditions. Thus, the proposed Class-EFJ PA features a simplified design and a miniaturized layout, enhancing integration. A schematic of the PA is shown in Figure 8, and Figure 9 is a photograph of the prototype PA module. It is a compact 45 × 56 mm.

Figure 8

Figure 8 PA schematic.

Figure 9

Figure 9 PA prototype.


SIMULATED AND MEASURED RESULTS

The prototype PA is driven up to 30 dBm for the measurements by CW signals at room temperature (see Figure 10). An output power of 40.7 to 42.5 dBm and a gain of 10.7 to 12.5 dB are realized from 0.6 to 3.3 GHz. Saturated drain efficiency (DE) is between 60.7 and 72.1 percent in that band as well.

Figure 10

Figure 10 Simulated and measured DE, output power and gain.

Figure 11

Figure 11 Measured PA linearity performance.


The measurements are consistent with the simulated values of output power and gain. Measured DE shows slight differences with the simulation over frequency, but is within the same range. The simulation model is designed with average load-pull data and other characteristics for the CGH40010F GaN HEMT family. Because the simulation model is not designed with the specific characteristics of the transistor used or test conditions, some small differences are expected.

Measured DE and gain versus output power at 0.9, 1.2, 1.5, 1.8, 2.1, 2.4, 2.7 and 3.0 GHz are shown in Figure 11. The saturated output power is 42.5 dBm at 1.8 GHz. The curves of gain versus output power are smooth, which is beneficial for linearity correction.

Table 1

Table 1 summarizes a performance comparison with recently reported PAs. This PA achieves a significantly wider fractional bandwidth than the referenced works. The Class-EFJ PA with this proposed structure offers a well-balanced combination of high efficiency and broad bandwidth.

CONCLUSION

This Class-EFJ PA uses a π-shaped matching network in the output matching circuit. The shunt element on the output of the π-shaped network is replaced by a compact structure composed of a pair of coupled microwave lines and a sectorial microwave stub. A broadband Class-EFJ PA is designed and fabricated based on this structure, which delivers over 40.7 dBm output power with 60.7 to 72.1 percent DE across a 0.6 to 3.3 GHz frequency band.

ACKNOWLEDGMENT

This work was supported by Project of Hangzhou Dianzi University Grant Number KYS045624199, Zhejiang Provincial Science and Technology Plan Grant Number 2024C01076 and Project of Ministry of Science and Technology Grant Number: D20011.

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