The first technology demonstration was implemented using the GlobalFoundries 45 nm RFSOI. The chip occupies a total area of 1.3 × 1.2 mm2 with a core area of 0.25 mm2.9 Figures 5 and 6 summarize the Dual-Drive PA’s continuous wave performance with different supply voltages (1.7 and 1.9 V), achieving a maximum OP1dB of 19.1 dBm at 31 GHz with less than 1 dB variation from 23 to 34 GHz.

Figure 5

Figure 5 Measured power gain and efficiency vs. output power of the initial technology demonstration (version 0) of the Dual-Drive PA at 30 GHz, biased at 1.9 (a) and 1.7 (b) V.

Figure 6

Figure 6 Large-signal CW measurements of the initial technology demonstration (version 0) of the Dual-Drive PA vs. frequency, biased at 1.9 (a) and 1.7 (b) V.

Figure 7

Figure 7 Measured single carrier, 64-QAM performance of the Dual-Drive PA, biased at 1.9 (a) and 1.7 (b) V.

Figure 8

Figure 8 Measured single carrier, 64-QAM constellation and spectrum performance of the Dual-Drive PA, biased at 1.9 (a) and 1.7 (b) V.

The Dual-Drive PA achieves a maximum PAE of 50 percent and maximum DE of 60 percent at 29 GHz. This is the highest reported efficiency for a two-stage CMOS PA in this frequency range. Moreover, a PAE greater than 40 percent is maintained across the entire bandwidth from 24 to 35 GHz.

The efficiency results are met with great linearity performance as well. For example, OP1dB and Psat are within 1 dB of each other, which translates to a maximum PAE at OP1dB of 47.4 percent. Excellent linearity is demonstrated through extensive modulation measurements shown in Figures 7 and 8. For example, for a 9 Gb/s 64-QAM signal without digital predistortion (DPD), the Dual-Drive PA achieves an average Pout of 15.1 dBm and average PAE of 30.2 percent with a -25 dB rms error vector magnitude at 30 GHz. The efficiency performance is maintained at supply voltage levels that are 20 percent lower than the rated supply voltage, which positions the technology for high reliability applications.

The first generation 30 GHz Dual-Drive PA using a 45 nm SOI process achieves 50 percent PAE for the two-stage proof-of-concept, which is the highest efficiency ever achieved for a two-stage PA at 30 GHz on CMOS. Falcomm has been further developing and maturing the technology and newer tested prototypes are reaching even higher efficiencies with PAE reaching the 55 percent mark for a two-stage PA and average PAE of 34 percent using a 9 Gb/s 64-QAM signal at 30 GHz, which is a higher average efficiency than a Doherty PA can offer but with half the Si area.


Falcomm is focusing on developing its core technology into a product catalog with PAs of different power levels, frequency ranges, gain and packaging that will bring a better value to satellite, base stations and handheld device manufacturers. Falcomm believes these results demonstrate that its technology will become the industry standard for PAs and, based on current design efforts, is confident that it can push the technology further.


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