The Dual-Drive Power Amplifier: The Next Frontier in Power Amplification
The first generation 30 GHz Dual-Drive™ power amplifier (PA) using a 45 nm silicon on insulator (SOI) process achieves 50 percent power-added efficiency (PAE) for a two-stage proof-of-concept, which is the highest efficiency ever achieved for a two-stage PA at 30 GHz on CMOS.
The world’s dependence on wireless communications is ever increasing within our daily lives, spanning multiple industries such as automotive, health care, consumer products, space communications and travel, scientific and military. Powering these new opportunities in wireless communications is the PA, which enables wireless transmission of data around the world.
With a compound annual growth rate of ~12 percent, the $16 billion PA market is one of the main driving forces enabling the advancement in wireless communication systems.1 Falcomm is working toward radically improving PA products for the wireless communications market.
Modern PAs are expected to support high-order modulation signals (e.g., 256-/1024-/4096-QAM) with OFDM, increasing peak-to-average power ratio (PAPR) specifications. Yet, these high PAPR levels can lead to less than desired average PAE at output back-off levels given current PA topologies. Therein lies the issue where the PA serves both as the enabler and the limiter for the desired implementation of advanced communication systems.
While the PA can service such high-order modulation schemes, it may inefficiently consume most of the power budget within a given wireless communication system, where most of the wasted energy is dissipated as heat. Given the ever increasing stringent communication protocols and requirements, high performance PAs are of paramount importance in the successful and rapid adoption of commercial next-generation communication networks.
Increasing the efficiency of PAs can greatly benefit the entire wireless communication market, which includes mobile devices, wearables, cellular base stations, cellphones, radar and other emerging markets.
For example, cost of ownership for cellular base stations is becoming a bigger concern for network operators as the deployment of 5G mmWave infrastructure takes place. In 2021, network operators spent about $120 billion for electricity in cellular base stations, where more than 50 percent of the energy consumption was from inefficient PAs. Therefore, increasing the efficiency of PAs will directly translate to reducing the electricity bill and carbon footprint of the wireless network infrastructure.
Another frontier for next-generation wireless communications systems is in space, where there is renewed interest and a desire to expand the robust low Earth orbital (LEO) economy and deploy a satellite infrastructure for reliable communication networks (such applications are Wi-Fi from space, cellular access to remote locations and intra-space communication, to name a few) and maintain a constant human presence in LEO to facilitate the next generation of space travel.
While commercial spacecraft manufacturers like SpaceX have helped reduce rocket/payload launch costs to less than $2,000 per kilogram,2 these costs still pose a high barrier to entry for companies with emerging new technologies, and they incur additional expenses to government agencies like NASA. Falcomm’s customer interactions with satellite manufacturers found that battery and solar cell loads account for a significant portion of a satellite’s weight. In some cases of Earth-to-space communication modules within satellites, the PA can be responsible for nearly 80 percent of the energy budget.
A more efficient PA can greatly ease thermal management requirements and reduce battery and solar cell sizes, but most importantly it can lower manufacturing and launch costs for satellites. For example, a micro-geostationary orbit (GEO) satellite manufacturer estimates that every 10 percent increase in PA efficiency will translate to $150,000 of launch cost savings per spacecraft due to the reduction in battery and solar cell weight. The estimated savings do not include the reduction in manufacturing and thermal management costs due to higher PA efficiency.
EXISTING PA TOPOLOGIES
The demand for more efficient and more linear PAs has driven extensive research to improve performance at the device level, for example increasing the fmax/ft of the transistor.3 In addition, improvements in the back end of the line processes such as thicker and lower-loss top metal layers have increased the performance of passive components, which has allowed a further increase in efficiency and output power.4
The increased fmax/ft metrics of the transistor device, however, do not necessarily lend themselves to improved PA performance, as, typically, the smaller lithography nodes have reduced voltage supply overhead and smaller breakdown limits, making apparent the tradeoff in device performance and reliability.
With regard to circuit topology improvements, to this date, almost all PA designs rely on common-source or common-gate topologies and are mainly focused on increasing peak/power-back-off (PBO), PAE and maximum output power (Pout) by presenting multi-harmonic terminations to the output of the PA, as accomplished in the Class F, Class J and their inverse and continuous-mode operations.5
A topology that has gained popularity in recent years is the harmonic-tuned PA and its different variations. This topology takes advantage of adding load terminations at the fundamental frequency and at some of the harmonics to increase the maximum PAE of the amplifier. Most modern technology nodes exhibit an fmax/ft between 100 and 300 GHz; therefore, at mmWave frequencies, the harmonic content might not be substantial enough to make a major improvement in efficiency. Additionally, passive networks that can provide harmonic tuning tend to be complex and lossy, further reducing the efficiency enhancement. Even though this technique shows low to moderate efficiency improvements, the beforementioned drawbacks hinder its adoption in commercial applications.
Recent efforts have also focused on further improving efficiency based on circuit topologies that can support complex modulation methods, such as stacked, outphasing, mixed-signal, reconfigurable and Doherty PAs.6,7 However, in modern Si processes with nanometer sized technology nodes that employ supply voltages of less than 1 V per stacked transistor (2 V for cascode devices), these reported techniques see diminishing returns on PAE and Pout since the transistor knee voltage, Vknee, becomes a significant portion of the supply voltage. Moreover, an extra reduction in supply voltage is often observed in practical deployment to ensure device reliability.
This is especially relevant for mmWave array operations, where array element couplings result in substantial antenna impedance mismatches (VSWR) and undesired large PA output voltage/current swings. Although the reported techniques have improved overall PA efficiency at mmWave frequencies, their operating principles are incapable of theoretically surpassing the linear mode operation PA core efficiency of the Class B common-source topology without resorting to lower conduction angles or harmonic shaping.
Beyond solid-state technology, traveling wave tube (TWT) amplifiers have been commonly used in satellite transceivers due to their high-power capabilities and high efficiencies (greater than 90 percent). However, TWT amplifiers are extremely bulky with form factors spanning several tens of centimeters and cannot support modern communication systems due to the reduced antenna size and spacing requirements of array-based architectures at higher frequencies (greater than 1 GHz).
Therefore, ultra-efficient high-power millimeter-sized solid-state PAs are critical for the successful and rapid adoption of next-generation communication networks since they are superior to other alternatives in transceiver power efficiency, thermal management requirements and overall communications channel performance.
EFFICIENCY CONSIDERATIONS FOR PAs
Figure 1 shows Psat versus PAEmax for previously published PAs ranging from 20 to 50 GHz.8 There is an inherent tradeoff between Psat and PAEmax. In addition, there exist two distinctive power/efficiency regions for PAs delimited by Psat. In the red region, called the device limited regime, efficiency is limited by the technology or device performance characteristics and to some extent by the design topology.
In the blue region, called the circuits/combiner limited regime, an increase in power is attained by employing different power combining techniques and, therefore, efficiency is limited by the losses of the output combiner network. This shows a clear tradeoff between saturated output power and maximum efficiency.
Moreover, when considering energy efficiency in PAs, PAE can be characterized by the four independent factors shown in the following equations:
where the first factor (FVmin) is associated with the maximum allowed output voltage swing, which is determined by the knee voltage of the device and the supply voltage; the second factor (FGain) is related to the gain of the device or the necessary driving power needed to saturate the PA; the third factor (FMatching) relates to the passive efficiency of the output network and the last factor (FWaveform) is a constant that depends on the PA gate biasing.
From these definitions we can conclude that the first two factors, FVmin and FGain, are limited by the device choice, while the last two factors, FMatching and FWaveform, are limited by design choices. Previous topologies aimed at improving the maximum efficiency of the PA were limited to only increasing FMatching and FWaveform through design choices.
CLASS B PA THEORETICAL EFFICIENCY REVIEW
In Class B operation, the transistor is biased at the threshold voltage (VTH) and only conducts current during half of the cycle. When the device is on, the drain current is proportional to (Vin – VTH). Therefore, the drain current can be modeled as a half-wave rectified sine wave. Although the transistor drain current has large frequency content, the passive output network ensures that only the fundamental tone reaches the load. Using Fourier series analysis, we can define the maximum output power as:
The peak voltage swing at the load, Vpeak, can be described in terms of the supply voltage, VDD, and the knee voltage, Vknee, to include the effects of the device choice:
The DC power dissipation of the transistor can be expressed using the maximum current going through the load, Imax, as shown in the following equations:
Finally, the maximum theoretical drain efficiency (DE) of an amplifier operating in Class B mode can be expressed by combining equations (6) through (9), as shown in equations (10) through (13).
Equation (13) shows the canonical Class B maximum efficiency of 78.5 percent when the Vknee is zero. In addition, Equation (13) also establishes the relationship between Vknee and the DE, ηclass-B, as previously shown using the proportionality constant FVmin in Equation (1).
The new patented Dual-Drive™ topology enables additional design freedom in improving PA performance by artificially reducing the knee voltage of the device, increasing the factor FVmin and in turn increasing the overall PAEmax of the PA. When a transistor is only driven at the gate, the device maximum efficiency is dictated by the device conduction angle and the knee voltage, Vknee. Vknee indicates the transition region between the linear and saturation region of a transistor and is a technology-specific physical parameter inherent to the physical device’s fabrication process and size. Moreover, Vknee reduces the output voltage and drastically impacts the achievable DE and overall efficiency of a PA.
In the Dual-Drive™ topology, Falcomm exploits the transistor as a three-terminal device and drives both the gate and the source terminals with out-of-phase inputs Vin and αVin (0<α<1), as shown in Figure 2. Assuming short terminations for all harmonics at the drain node, the source voltage now swings below ground while having an in-phase relationship with the drain voltage, increasing the maximum drain output voltage swing by αVin. This increased output voltage swing can be attained without increasing the supply voltage, which means that the maximum DE is increased in the Dual-Drive™ topology by a factor greater than 1.
Falcomm demonstrated for the first time that through the Dual-Drive PA architecture they are able to artificially reduce/cancel out the knee voltage of the transistor, allowing for the maximum theoretical efficiency of a PA to be fundamentally increased beyond that of any PA class and topology as shown in Equation (14).
When the maximum voltage swing at the source is equal to the knee voltage of the transistor (αVin=Vknee), the theoretical maximum DE for the Dual-Drive PA will reach the maximum theoretical efficiency of the class B PA, π4, as shown in Equation (15).
The strength of the source swing depends on α, which is a design constant that can be adjusted. Figure 3 shows that with varying α, there is a tuning tradeoff for PA designers to balance between power gain and the achievable efficiencies of the Dual-Drive PA transistor core. These results show that by employing the Dual-Drive architecture, the efficiency lost by the Vknee of the transistor can be recovered. In addition, Falcomm’s analysis of the Dual-Drive PA is consistent with Equation (1).
BENEFITS OF THE DUAL-DRIVE PA
The benefits of the Dual-Drive PA topology are summarized as follows: first, increasing the source terminal coupling coefficient, α, can fundamentally increase the PA core DE beyond that of any other PA topology; second, higher DE can be maintained even at reduced supply voltages since the effect of Vknee under a lowered supply can be mitigated and third, the maximum output power can be increased while reducing the device modulation distortion, since the active device spends more time in its saturation region and less in triode.
Furthermore, the parallel input resistance of the transistor is reduced since the typically large device gate impedance is combined in parallel with its low device source impedance, aiding the design of broadband and low loss inter-stage matching networks without the need to implement lossy de-Qing resistors.
Finally, the Dual-Drive PA can mitigate the reliability issues of voltage peaking typically seen in complex harmonic-shaping PAs (Class J or continuous-mode Class F PAs). Therefore, the Dual-Drive PA is particularly suitable for high reliability space applications that mandate consistent operation in harsh environments while achieving ultra-high efficiency levels.
Initial efficiency measurement results from Falcomm’s first and second generation low-power CMOS Dual-Drive PA prototypes in comparison with state-of-the-art PAs at the same frequency band are shown in Figure 4. These initial results demonstrate that the Dual-Drive PAs are at least 25 percent more efficient than conventional PAs; which, based on estimates and discussions with one of Falcomm’s potential customers building micro-GEO satellites, could translate into $350,000 in launching cost savings per satellite.
DUAL-DRIVE PA SUPERIOR PERFORMANCE
The first technology demonstration was implemented using the GlobalFoundries 45 nm RFSOI. The chip occupies a total area of 1.3 × 1.2 mm2 with a core area of 0.25 mm2.9 Figures 5 and 6 summarize the Dual-Drive PA’s continuous wave performance with different supply voltages (1.7 and 1.9 V), achieving a maximum OP1dB of 19.1 dBm at 31 GHz with less than 1 dB variation from 23 to 34 GHz.
The Dual-Drive PA achieves a maximum PAE of 50 percent and maximum DE of 60 percent at 29 GHz. This is the highest reported efficiency for a two-stage CMOS PA in this frequency range. Moreover, a PAE greater than 40 percent is maintained across the entire bandwidth from 24 to 35 GHz.
The efficiency results are met with great linearity performance as well. For example, OP1dB and Psat are within 1 dB of each other, which translates to a maximum PAE at OP1dB of 47.4 percent. Excellent linearity is demonstrated through extensive modulation measurements shown in Figures 7 and 8. For example, for a 9 Gb/s 64-QAM signal without digital predistortion (DPD), the Dual-Drive™ PA achieves an average Pout of 15.1 dBm and average PAE of 30.2 percent with a -25 dB rms error vector magnitude at 30 GHz. The efficiency performance is maintained at supply voltage levels that are 20 percent lower than the rated supply voltage, which positions the technology for high reliability applications.
The first generation 30 GHz Dual-Drive PA using a 45 nm SOI process achieves 50 percent PAE for the two-stage proof-of-concept, which is the highest efficiency ever achieved for a two-stage PA at 30 GHz on CMOS. Falcomm has been further developing and maturing the technology and newer tested prototypes are reaching even higher efficiencies with PAE reaching the 55 percent mark for a two-stage PA and average PAE of 34 percent using a 9 Gb/s 64-QAM signal at 30 GHz, which is a higher average efficiency than a Doherty PA can offer but with half the Si area.
Falcomm is focusing on developing its core technology into a product catalog with PAs of different power levels, frequency ranges, gain and packaging that will bring a better value to satellite, base stations and handheld device manufacturers. Falcomm believes these results demonstrate that its technology will become the industry standard for PAs and, based on current design efforts, is confident that it can push the technology further.
- “RF Power Amplifiers – Global Market Trajectories & Analytics,” Research and Markets, April 2021, Web: www.researchandmarkets.com/reports/5141446/rf-power-amplifiers-global-market-trajectory.
- I. Williams, “Boost-Phase Missile Defense Interrogating the Assumptions,” Center for Strategic and International Studies, June 2022, Web: www.csis.org/events/boost-phase-missile-defense-interrogating-assumptions.
- S. Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner and J. Kim, “Record RF Performance of 45-nm SOI CMOS Technology,” IEEE International Electron Devices Meeting, December 2007, pp. 255–258.
- O. Inac, M. Uzunkol and G. Rebeiz, “45-nm CMOS SOI Technology Characterization for Millimeter-Wave Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 62, No. 6, June 2014, pp. 1301–1311.
- S. C. Cripps, P. J. Tasker, A. L. Clarke, J. Lees and J. Benedikt, “On the Continuity of High Efficiency Modes in Linear RF Power Amplifiers,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 10, October 2009, pp. 665–667.
- S. Hu, F. Wang and H. Wang, “A 28-/37-/39-GHz Linear Doherty Power Amplifier in Silicon for 5G Applications,” IEEE Journal of Solid-State Circuits, Vol. 54, No. 6, June 2019, pp. 1586–1599.
- E. F. Garay, D. J. Munzer and H. Wang, “26.3 A mm-Wave Power Amplifier for 5G Communication Using a Dual-Drive Topology Exhibiting a Maximum PAE of 50 Percent and Maximum DE of 60 Percent at 30 GHz,” IEEE International Solid-State Circuits Conference, February 2021, pp. 258–260.
- 8.H. Wang, T. -Y. Huang, N. Sasikanth Mannem, J. Lee, E. Garay, D. Munzer, E. Liu, Y. Liu, B. Lin, M. Eleraky, H. Jalili, J. Park, S. Li, F. Wang, A. S. Ahmed, C. Snyder, S. Lee, H. T. Nguyen and M. E. D. Smith, “Power Amplifiers Performance 2000-Present,” Georgia Tech Electronics and Micro-System Lab (GEMS), August 2021, Web: https://gems.ece.gatech.edu/PA_survey.html.
- E. F. Garay, D. J. Munzer and H. Wang, “A 150 GHz Lens-Free Large FoV Regenerative 2 × 2 Transceiver Array With 31 Percent DC-to-EIRP Efficiency and −70 dBm Sensitivity for a 70 cm Bidirectional Peer-to-Peer Link,” IEEE Journal of Solid-State Circuits, Vol. 57, No. 7, July 2022, pp. 2102–2113.