Goodman11 proposed an interleaved version of his model, and a conceptual diagram is shown in Figure 5. Each branch has its own NLEQ, so the computations of the finite impulse response (FIR) filters are polyphase and run at 1/N of the RF sample rate. Experimental results from Goodman11 show 20 dB of SFDR improvement but there is a severe computational complexity cost. Approximately 200 multiply/adds per RF sample are needed, verified using actual commercial ADCs.

Figure 5

Figure 5 Goodman’s all-digital polyphase NLEQ conceptual diagram.11

It takes thousands of training passes consisting of two- or three-tone tests to accumulate the optimum Volterra coefficients for the filters. The user should be aware that if the input signal conditions during the application do not match up with the training signals that determined the Volterra coefficients, then performance could be dramatically diminished.

The whole point of an extremely wideband RF ADC is to run at a highly oversampled condition to capture input signals in the most flexible digital manner possible. One must consider the assumptions of an initial training, including the center frequency of the carrier constellation relative to RF Nyquist, the bandwidth of the modulation, and the modulation characteristic itself.

Assume that the Volterra coefficient adaptive training was done at the high rate prior to the digital down-converter (DDC), say, 50 GSPS. Then roughly a 10 teraflops computation rate is needed. Now assume that the training was done at a decimated rate of 8 GSPS after the DDC. This would result in a 1.6 teraflops computation rate, far more practical to implement in hardware. The downside is that the down-converted and decimated signal throws away potentially valuable nonlinear information that would be valuable for an accurate adaptation.

For example, IM3 distortion from out-of-band blockers at higher frequencies as seen at the undecimated higher rate will potentially fold into the desired baseband and defeat the purpose of NLEQ. It seems that RF-rate NLEQ may be altogether unavoidable, which reverts back to the multi-teraflop computational complexity problem.

As for implementation, assume that the maximum multiply/accumulate rate for a dedicated hardware multiplier, such as 12 nm technology, is roughly 1 GHz. If it is assumed that part of the computations are in the FIR filters, and part in the least mean squared (LMS) adaptation and update steps, then there may be as many as 1,000 hardware multiply/accumulate units on-chip.

Some may view this as overly pessimistic. Assume that only the FIR filters are always running but the LMS adaptation update is turned off once it has ‘converged,’ then this results in a lower computational complexity problem during the actual application.

For example, assume 32 ADC branches each with a fifth-order polyphase NLEQ FIR filter, then there are 160 multiply/accumulate units per RF cycle, each running at 1/N rate, or maybe twice that number, resulting in a rate of at least 300 flops per RF cycle. Assume further that it takes roughly 20,000 transistors to implement a full 16 x 16 multiplier with a 36-bit accumulator. Then there are roughly 6 million transistors, not including the registers and state machines running the filters. The actual number for a dedicated NLEQ machine approaches 10 million transistors. That may become more reasonable as ADCs advance into a technology such as 3 nm.

At the time of this writing, there is one known example of an RF data converter that resides monolithically within a field programmable gate array (FPGA),12 and yet its sample rate is limited to 4 GSPS, far below the fastest RF data conversion chips sampling at 50 GSPS or higher.

A co-packaged FPGA and RF data converter has been offered by Intel.13 The RF data converter is based on the work of Hornbuckle,14 which disclosed that NLEQ is used to help produce an SFDR of 73 dB at 32 GSPS. Neither Intel nor Hornbuckle provides any information on the NLEQ processing. As for the performance, there is no ‘before’ and ‘after’ NLEQ comparison. It would be important to know what the ‘raw’ ADC produces with NLEQ turned off.

More questions yet remain as to the SFDR improvement when input signal conditions are changed without re-training and adaptation. Also, neither Intel nor Hornbuckle provide any details on the additional power consumption required to run the NLEQ processing in real time or on the requirements of the FPGA needed for the NLEQ processing. The Hornbuckle chip has its origins in an RF ADC chip from Kull et al.15 where the reported SFDR was 46 dB.

If NLEQ is factored into the system, a new metric is needed for FOM and SWAP-C, which includes the power consumption and cost factor of the NLEQ under a given condition and a given level of performance improvement. If NLEQ processing resides in a separate FPGA, the power consumption of the FPGA, as well as the cost, may be out of reach for most applications.

The highest-rate RF data conversion chips consume at least an order of magnitude less power than the most advanced FPGAs, e.g., 15 W vs. 150 W. The FOM of the combined parts is an order of magnitude greater than the data converter alone. The cost is likely far more than the linear sum of a separate RF data converter and an FPGA, due to packaging, testing and yield complexities. This implies that the SWAP-C also rises due to power and cost.

It also implies the combined parts will need special heat dissipation packaging with a fan, like an FPGA, where an RF data converter alone may not need a fan, per se. Even if power and cost were acceptable, a customer would have to experiment with training and adaptation for the particular bandwidth and modulation required. Assuming these power obstacles were tenable, then the cost of integrating an FPGA with an RF data converter into a net cost-effective lower-power product is a major challenge.

The power and cost factors improve with technology scaling, but ultimately an NLEQ computational engine will need to be on-chip with the ADC, made possible in a fine line technology node such as 3 nm. Since the computational engine executing the NLEQ would be in a dedicated architecture on-chip with the RF ADC, it would be far more efficient than if it were executed in an FPGA or even a separate ASIC. The high speed RF digital data sampled by the ADC would not need to be bussed off-chip.

The final hurdle will be what the customer must do to apply NLEQ to a system solution. Since the customer knows the application best, e.g., the constraints of the sampling frequency, the bandwidth, the type of modulation and interfaces, will the customer develop the procedure to train and adapt the NLEQ?

Finally, there are numerous patents or applications on NLEQ as applied to RF ADCs and analog receivers. A sampling is provided in the references.16-21


Our understanding of RF ADCs and their relevant performance metrics has evolved to the point where simple sine wave testing for ENOB and SFDR is no longer adequate to describe their behavior in a meaningful and comprehensive way. It is altogether too easy to apply simple adaptive methods that remove nearly all unwanted spectral artifacts from single- and two-tone input tests to produce nearly perfect SFDR results.

Such NLEQ adaptation is dependent on both frequency and bandwidth. Change these parameters and then re-adapt! Make it general enough to cover all useful frequencies and bandwidths and input modulation types, and the result will be a computational complexity level that is too high for most applications.

The question remains, is the SWAP-C is worth the processing penalty to the customer? In some cases it is, while in others it is not. The training for a given application must be mastered by the customer and it will not be one situation that fits all. Transparency is urged for the suppliers of these new types of RF ADCs to better inform their customers of these complex tradeoffs.

The first supplier to conquer the overall monolithic solution of ADC+NLEQ that eliminates most of the nonlinearities in an otherwise uncompensated system, and does it in a process such as 3 nm technology, will be a potential winner.


  1. S. Norsworthy, “RF Data Conversion for Software Defined Radios,” IEEE 20th Wireless and Microwave Technology Conference (WAMICON), April 2019.
  2. “IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters,” IEEE Std 1241-2010 (Revision of IEEE Std 1241-2000), January 2011, pp.1-139.
  3. W. Kester, “ADC Noise Figure – an Often Misunderstood and Misinterpreted Specification,” Analog Devices, MT-006 Tutorial, Rev. B, April 2014, pp. 1-9.
  4. A. Buchwald, “Specifying and Testing ADCs,” IEEE ISSCC, Tutorial, February 2010.
  5. A. Arrants, B. Brannon and R. Reeder, “Understanding High Speed ADC Testing and Evaluation,” Analog Devices, Application Note AN-835 Rev B, pp. 1-28.
  6. J. Karki, “Calculating Noise Figure and Third-Order Intercept in ADCs,” Texas Instruments Data Acquisition Journal,  2003, pp. 1-16.
  7. B. Annino, “SFDR Considerations in Multi-Octave Wideband Digital Receivers,” Analog Dialogue, Vol. 55, No. 1, January 2021. 
  8. T. Neu, “Clocking the RF ADC: Should You Worry About Jitter or Phase Noise?,” Texas Instruments Analog Applications Journal,  2017.
  9. B. Murmann, “ADC Performance Survey 1997-2022.” Web.,
  10. A. M. A. Ali, H. Dinc, P. Bhoraskar, S. Bardsley, C. Dillon, M. McShea, J. P. Periathambi and S. Puckett, “A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration,” IEEE Journal of Solid-State Circuits, Vol. 55, No. 12, December 2020, pp. 3210-3224.
  11. J. Goodman, B. Miller, M. Herman, G. Raz and J. Jackson, “Polyphase Nonlinear Equalization of Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of Selected Topics in Signal Processing, Vol. 3, No. 3, June 2009, pp. 362-373.
  12. “Zynq UltraScale+ RFSoC,” Xilinx, Web.
  13. “Eagle Summit” FPGA with Integrated RF Data Converter,” Intel, Web.
  14. C. Hornbuckle, “Ultra-High Speed Analog-to-Digital Converters in 14nm FinFET Process and Usage in Digital and Hybrid Phased Array Systems,” GoMACTech Conference, March 2018, pp. 504-510.
  15. L. Kull, D. Luu, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, A. Cevrero, Ilter Özkaya and T. Toifl, “A 24-72-GS/s 8-b Time-Interleaved SAR ADC with 2.0-3.3 pJ/Conversion and > 30 dB SNDR at Nyquist in 14-nm CMOS FinFET,” Journal of Solid State Circuits, Vol. 53, No. 12, December 2018, pp. 3508-3516.
  16. G. M. Raz and C. P. Chan, “Method and System of Nonlinear Signal Processing,” U. S. Patent 7 609 759, October 27, 2009.
  17. R. J. Velazquez and S. R.Velazquez, “Adaptive Digital Receiver,” U. S. Patent 9 118 513, August 25, 2015.
  18. S. R.Velazquez and R. J.Velazquez, “Linearity Compensator for Removing Nonlinear Distortion,” U. S. Patent 9 160 310, October 2015.
  19. S. R.Velazquez, “Compensator for Removing Nonlinear Distortion,” U. S. Patent 9 705 477, July 2017.
  20. S. R. Velazquez and Y. Wang, “Multi-Dimensional Compensator,” U. S. Patent 10 911 029, February 2021.
  21. H. H. Kim, A. Megretski, Y. Li and K. Chuang, “Digital Compensation for a Non-Linear Analog Receiver,” U. S. Patent 9 564 876, February 2017.