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Xilinx, Inc. has expanded its RF system on a chip (SoC) product family, initially introduced to support 5G development and production, cable broadband, radar and other high performance applications. The Zynq® UltraScale+™ RFSoC architecture integrates RF data converters and soft decision forward error correction (SD-FEC) blocks with high performance, programmable logic and an ARM® A53 multi-processing system into a 16-nm SoC that reduces board footprint and power consumption by 50 to 75 percent.

For cable broadband networks, distributed access architectures are moving physical layer (PHY) functions from the central headend to locations closer to consumers. With RF integration and an integrated, programmable SD-FEC signal chain, the RF SoCs meet remote PHY requirements, including the spectral efficiency prescribed by DOCSIS 3.1.

For radar—particularly active phased arrays—the Zynq UltraScale+ RF SoCs provides the low latency and digital signal processing needed for rapid turnaround from detection to transmission, together with power, footprint and cost advantages from the improved performance-per-watt capabilities of 16-nm FinFET+ technology.

As 5G massive multiple-input-multiple-output (MIMO) transceivers will incorporate a large number of antennas—from 32 to more than 1,000—the bill of materials and layout simplification using Zynq UltraScale+ is significant. An integrated SoC platform dramatically reduces the design complexity and power associated with moving data between the RF and digital front-ends.

Devices in the RFSoC family offer eight, 4 GSPS or 16, 2 GSPS, 12-bit analog-to-digital converters; eight or 16, 6.55 GSPS, 14-bit digital-to-analog converters; integrated SD-FEC cores with low-density parity-check and Turbo codecs; a multi-core ARM A53 processing subsystem; 16-nm UltraScale+ programmable logic; up to 930,000 logic cells and over 4200 DSP slices.

Xilinx Inc.
San Jose, Calif.