A Small CDMA Module for Wireless PCS Handsets

Warren, NJ

The rapid growth of wireless handsets has created pressure on RF design engineers to provide feature-rich, timely solutions that allow market success. Time to market from concept to volume ramping for production has become a key issue in the industry. The semiconductor technologies used for RF power amplifiers in today’s wireless telephones have not solidified into a single definitive solution due to the many factors a designer is forced to trade off to simultaneously meet cost, size, performance, modulation scheme and time-to-market requirements now measured in months. Regardless of the semiconductor device technologies used (MESFET, pseudomorphic high electron mobility transistor, GaAs heterojunction bipolar transistor (HBT), SiGe HBT or Si BJT), amplifier designs must be cost effective and compact, offer competitive performance and be simple to implement.

Advances in MMIC and multichip module (MCM) technologies have allowed the design of a small (7 x 7 mm) MESFET-based power amplifier for low voltage CDMA PCS handset applications. The high levels of integration of GaAs MESFETs allow this small module to incorporate an internal negative generator, sequencing circuit for turning on the drain switch, temperature-compensating bias networks and an Intelligent Power Management™ scheme. A drain supply MOSFET switch along with 50 W input and output matching networks are included in this module.

Design Features

The design and construction of the model AMT6101 MCM for PCS CDMA handsets requires simple bypass capacitors and no major external components or impedance matching. The RF engine of this module is an ion-implanted GaAs MESFET MMIC. Semi-insulating high resistivity GaAs substrates allow passive matching components to be fabricated on the die, reducing the number of surface-mount components used in the module. High performance GaAs MESFETs are depletion-mode devices and require a negative voltage to turn off the device. A DC-to-DC voltage conversion circuit is employed to create the required negative voltage from an available regulated positive system voltage. Additionally, a power supply sequencing circuit and MOS pass transistor complete the design to form a comprehensive, self-contained module solution for telephone designers. This sequencing circuit controls the gate of the MOS pass transistor and inhibits the drain voltage when the negative voltage is not present.

A major design goal for this module was to simplify the PCS phone design cycle by providing both a simple RF and DC module solution. A block diagram is shown in Figure 1 , outlining the functionality of this module design. The heart of the module is the power amplifier MMIC, which provides 28 dBm of linear power. Input and interstage matching circuits optimize performance of this amplifier across the 1850 to 1910 MHz band at 3.5 V. Table 1 lists the device’s key features and performance levels.

Table I
Key CDMA MCM Amplifier Design Features

Size (mm)

7 x 7 

Input/output impedance ()W


Primary/secondary (V)


Self-sequenced supplies

no order required

Low leakage (off state) (µA)


Quiescent current  (no RF) (mA)


Operating frequency (MHz)

1850 to 1930

Power output (dBm)


Efficiency(%) at Pout = +28.5 dBm


Low power efficiency(%) at Pout = +28.5 dBm


Power gain at Pout = +28.5 dBm


An on-chip active bias circuit has been utilized to provide bias stability over temperature and across process variations. Additionally, a dynamic bias circuit improves performance of the amplifier at high drive levels and improves its distortion characteristics while allowing low quiescent currents to be set. These low quiescent currents have a direct effect on the efficiency of the amplifier at low power levels, which statistically can be the average operating point for a CDMA telephone. The on-chip Intelligent Power Management circuit allows the bias circuit’s set point to be a function of the output power and to shift to a more favorable operating point at high transmit levels.

Substrate and MMIC Design

Electrical and thermal design of the ceramic substrate was performed in parallel with the GaAs chip. This procedure allowed the overall module footprint to be significantly reduced by partitioning those components best integrated into the die and those best suited to place on the ceramic substrate as either printed or surface-mount components. The goal was to develop a package outline of 7 x 7 mm and a height of 2 mm or less, which was achieved.

While the quality factor of inductors fabricated on a semi-insulating GaAs substrate can exceed 15, optimum performance is achieved by leaving the RF chokes on the ceramic substrate. Low frequency bypass capacitors required for proper stability are relatively large and are best placed on the ceramic substrate due to their large realizable capacitance densities, which can be achieved with surface-mount materials. The input, interstage, DC-to-DC converter, supply sequencing and active bias circuits reside on the die. A high side PMOS switch is placed on the ceramic substrate. Its gate terminal is controlled by the sequencing circuit, which turns off the voltage to the power amplifier when no negative voltage is present on the gates or when power down is required. This PMOS device has an off-state leakage level of 2 mA and provides a low on resistance when switched on by the sequencing circuit. The supply sequence control circuit has a fast response time of less than 10 ms as shown by the timing diagram in

Figure 2 , which cycles the positive voltage to the DC-to-DC converter and monitors the respective gate (Vg3) and drain (Vpa) voltages of the amplifier.

The input of the RF amplifier is matched to 50 W with on-chip elements. A 50 W output matching circuit was optimized with a series-L/shunt-C transformation network. The active die was designed using the LIBRA™ harmonic balance simulator tool, which provided a solution for large-signal terminations at both the fundamental and its harmonics. Proper choice of both matching and bias elements allowed realization of the desired impedance characteristics vs. frequency. Figure 3 shows the module’s Pout and power-added efficiency (PAE) vs. Pin at the center of the PCS transmit band with CDMA modulation. The associated linearity is shown in Figure 4 , which displays the adjacent-channel power at a +28 dBm output power level.


This small PCS module has been designed and developed to demonstrate state-of-the-art performance and size capabilities. The RF handset designer can utilize the features incorporated in this module to introduce a product to the market in a short time period. This RF amplifier module utilizes established MMIC technologies and conventional surface-mount techniques that can be supplied in high volumes rapidly to allow longer run rates for an existing telephone platform before replacement with the next generation. Additionally, this RF transmit design solution can be used across multiple models to allow further cost savings with the added volume.

Warren, NJ
(908) 668-5000.