The demand for mobile communication devices has grown dramatically in recent years, further taxing an already difficult design process. Adding to the stress is the need for multi-standard support at higher and higher data rates and new applications at mm-wave frequencies. Product form factors are shrinking and designs must be lower cost, have a tighter power budget and higher electrical performance. Just as critical, those designs and subsequent products are being constrained by shrinking design cycles.
The main challenge is no longer the implementation of the RFIC itself, but its integration into the overall system—which could be a single package, some type of chip-level wafer-scale package, or a module/System-in-Package (SiP)—while still ensuring that the system meets tight performance requirements when measured on a reference board. Addressing these challenges requires a holistic approach with a complete, interoperable tool flow and design methodology; one that provides enough flexibility to accommodate the varying integration types, underlying process technologies and customer-specific design constraints that may change from one product generation to the next or across applications.
An Interoperable Co-Design Flow
Traditionally, MMIC and silicon RFIC designers have worked independently. Their designs have been created, simulated, implemented, and verified separately using different tools, methods and flows. Cadence Virtuoso is a widely used platform for silicon-CMOS design, especially for larger analog/mixed-signal applications. Keysight ADS is a leading tool for gallium-arsenide (GaAs) and gallium-nitride (GaN) MMIC design.
While there is already a need to interface between the two worlds, the move from III-V materials to silicon for components (e.g., antenna switches in CMOS-SOI) and the increase in mm-wave silicon applications for wireless HDMI and radar, further blurs the boundary between these tools and the specific jobs for which they should be used. Which tool to use and when was previously determined by a variety of factors, including: designer preference, process design kit (PDK) support, circuit type, or even just historical factors like what the designer may have used in the past and whether that experience was a good one, rather than how the designer might best accomplish a given task.
A one-size-fits-all tool is not realistic given the breadth of applications and processes. Going beyond the IC level, the need for solutions across design domains becomes even more obvious. Conventional IC layout tools are 2D and only allow a single (silicon) substrate carrier for drawing devices and interconnects, while a tool like ADS enables multi-technology design and the integration of parameterized 3D components.
In order to provide the best design support at any given time, a true interoperable co-design flow is required. What is co-design? Simply put, a co-design environment allows the designer to validate and optimize the overall system, including the interfaces between the connected components (e.g., IC-to-IC, IC-to-package or package-to-board).
In the past, a great deal of effort was spent integrating a certain capability (tool) into a widely used platform or providing import/export links between the two environments. Several years ago, however, OpenAccess was introduced as a new common database for custom IC design. Since then it has become the de-facto standard, with most EDA vendors now supporting it. Additional efforts like the introduction of iPDKs have followed with the goal of enabling interoperability between EDA tools.
These efforts have provided tools like ADS and Virtuoso enhanced interoperability, and enabled them to present designers with a true interoperable co-design flow. Using this flow, designers working at the schematic level can now open a single OA schematic view in Virtuoso or ADS, modify it, simulate it, and then bring it up again in the other environment. At the layout level, designers can open a Virtuoso layout view in ADS, assuming the SKILL pcells are flattened.
Now the question is: How does this help designers address the challenges associated with designing today’s wireless front-ends? To answer that question, we’ll show three different examples of how RFICs are currently being integrated (an RFIC in a QFN package, a flip-chip wafer-level chip-scale package and an RF module) and how the proposed interoperable co-design flow can be used to address them. All three examples have the same design requirements.
Validating an RFIC, Including QFN Package and Board Effects
RFICs are typically put in surface mount technology (SMT) packages with maximum operating frequencies of up to about 45 GHz. The most popular package style for radio and microwave frequency ICs is the quad flat no-leads (QFN) package.1At higher frequencies, the series inductance of the RF signal bond wires and the overall grounding inductance (IC, package and board) are two examples of the challenges designers need to consider.
Figure 1 shows the layout of a transceiver IC in Virtuoso. The pad ring, along with the top-level interconnects from the low noise amplifier (LNA) to the power amplifier (PA), are saved as a layout cellview in Virtuoso and opened in ADS. This part of the IC is put into a QFN package, which is available in ADS as a “pcell.” The designer does not need to draw any package layout other than adding the bondwires to the chip and placing it on a reference board that includes parameterized 3D models for connectors.
From the full configuration (shown as a 3D image from ADS), a 3D finite-element method (FEM) simulation is launched that captures the complete couplings in the resulting S-parameter file. An EM/circuit co-simulation could also be launched from the corresponding schematic test bench to minimize parasitic effects or optimize the grounding path, while considering additional coupling from the package, or how the matching at the RFIC outputs changes and would require circuit retuning.
Enabling Fan-Out Wafer-Scale-Package Co-Design
Wafer-level chip scale packages (WLCSP) are becoming more and more popular as a way to reduce RF parasitics and overall design size, while improving performance. In flip-chip wafer-level packages, solder balls are directly put on top of the silicon die and connected by metal traces in one or more re-distribution layers (RDLs.) This is then mounted directly onto the board with the surface of the die facing down. In so-called fan-in configurations, the resulting “package” is truly chip scale, while with fan-out, the die is embedded in a molding compound that allows a higher I/O count without being limited by the actual die size. Fan-out configurations also allow for multiple dies to be embedded within the molding compound and enable larger, more highly integrated systems.2
Figure 2 shows a layout of a fan-out wafer-level package CMOS IC along with two embedded inductors over the molding compound. Even without considering the 3D nature of the solder balls or taking the board into account, this configuration cannot be captured in a classical (2D) IC layout tool. The 3D view of an excerpt of a test structure, including true 3D solder balls and the test board, is also shown in Figure 2. Simulation results of the complete configuration confirmed a noticeable shift compared to simulations where the test structure needed to be split into an on-die and a molding area and without considering the solder balls or test board interconnects.
Implementation of an RF Module
RF front-end modules are a final example used to describe the design challenges of multi-technology systems in more detail. Figure 3 shows a typical PA module with 3 die—a GaAs HBT PA in a WIN process, Silicon-on-Insulator (SOI) transmit/receive switch in a CS18 process from TowerJazz and a control IC—on a 4-layer laminate with additional surface mount devices and embedded passives. The main design challenge here is to understand and address any potential problems coming from the interface between the IC technologies. Since design cycles are very short in the commercial wireless space, it is necessary to predict and solve these problems up front so that demanding product sampling schedules can be met.
Assume that the GaAs PA was implemented front-to-back in ADS and the digital control IC was implemented in Virtuoso. The RF section of the SOI switch was done in ADS in order to model the EM effects on the device, while the analog portion was done in Virtuoso. With the interoperability support described earlier, the RF module designer can now easily bring the design collateral together and co-design the system with full fidelity.
For example, the switch IC designer may design a circuit that meets a receiver isolation requirement, only to find out that at the module level, adjacent wire coupling degrades this isolation. The switch designer can now co-design the switch within the SOI and laminate technologies simultaneously; that is, the designer can investigate whether spacing of IC pads would help, if another series/shunt device should be added, or if a flip chip approach would yield better isolation.
An automated EM/circuit co-simulation flow, like that in ADS, makes it very efficient to mix and match different levels of the design hierarchy and manage what should be covered by the EM simulator or if existing schematic representations, models or even parasitic extracted views are being used. Also critical for such applications is an electro-thermal simulator, which provides “thermally aware” simulation results that account for thermal coupling between devices, as well as heat transfer through the die and packaging.
An important element of the flow is the efficient back-annotation of the extracted model or S-parameter data files to the top-level test bench for a parasitic re-simulation. As an example, Figure 4 shows the PA module top-level test bench in ADS with look-alike symbol for the laminate. Having all the design collateral in a single database not only allows quick setup and EM simulation, but also easy usage of the results across the design hierarchy, like capturing die to laminate interferences.
Based on the three different application examples presented, it is easy to understand why an interoperable co-design flow is so critical to confidently and efficiently designing RFICs and integrated packaging configurations. The design process manages the electrical and physical interfaces between design components across all of the associated design domains. In the future we will see continued trends toward increased integration, such as further PA module integration in SOI technologies, as well as tighter integration between front-end modules and transceivers. Despite this, the need for and importance of an interoperable, co-design flow does not go away. Instead, it becomes even more crucial. Use of this flow is the only way to reconcile aggressive time-to-market demands, complex cost structures and challenging tradeoffs in system architecture.
- L. Devlin, “The Future of mm-wave Packaging,” Microwave Journal, February 2014, pp. 24-38.
- C.C. Liu et.al. “High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,” Electron Devices Meeting (IEDM), IEEE International Conference, San Francisco, CA, 2012, pp. 14.1.1-14.1.4.
Juergen Hartung is the RFIC product marketing manager at Keysight EEsof. Previously he worked as the RFIC business development manager for Agilent in Europe. Prior to Keysight, he spent 10 years with Cadence Design Systems in RF/analog/Mixed Signal research, technical marketing, and as the director of engineering for wireless application design flow. Hartung started his career as an RF design engineer at SICAN GmbH in Germany. He holds a Masters and PhD in electrical engineering.