For mobile phones, WLAN and other wireless applications, RF engineers need to perform sophisticated IC designs under strict time-to-market constraints. To make this possible, with as few prototyping cycles as possible, RFIC design tools must incorporate efficient methods for analyzing circuit behavior, accurate semiconductor models and flexible system modeling capabilities.
Over the years APLAC analysis has been successfully applied at RFIC and system level design iterations for a broad range of complex design problems. Technology leaders use the company’s tools extensively in their RF design work, with the most commonly cited benefits being increased productivity, shorter design cycles, speed in running extremely large harmonic balance (HB) simulations for RFICs, and a more accurate match between simulated results and final product characteristics.
Now, however, there is the new APLAC Harmonic Balance algorithm and RFIC Design Link, demonstrating the use of accelerated HB analysis linking with third-party design frameworks. Real QPSK modulator and demodulator circuitry has been designed with both Cadence and Mentor Graphics IC design tools. This HB analysis algorithm will be part of the APLAC RFIC simulation module and the new APLAC RFIC Design Link that will be launched at European Microwave Week 2004.
Harmonic Balance Development
Nonlinear frequency domain methods are a vital component of tools used for the analysis of integrated radio circuits. Ten times more efficient than nonlinear time domain (transient analysis) methods, they quickly compute important performance indicators such as compression, noise and intermodulation. Especially important for RF applications, it is straightforward to study linear frequency-dependent distributed components such as transmission lines.
Methods for achieving nonlinear frequency domain results can be roughly categorized into two subgroups, methods for weakly or strongly nonlinear circuits. Weakly nonlinear methods like Volterra analysis are usually faster, but often fail to capture and predict the detailed nonlinear behavior of the system, such as what happens with higher levels of compression.
Probably the most used method for strongly nonlinear circuits is the harmonic balance method, which computes steady-state spectra and waveforms of strongly nonlinear circuits under periodic large signal excitation. Again, the simulations can be roughly divided into two subgroups, single-tone excitation runs and multi-tone excitation runs. With the former, the frequencies generated into the circuit are integer multiples of a signal at one frequency only. With multi-tone excitations, frequencies exist in the circuit at the sum frequencies of arbitrary integer multiples of two or more independent frequencies.
However, computational efficiency and memory limit the upper range of the available frequencies. The HB method evaluates nonlinear elements in the time domain and the linear elements in the frequency domain. All this data is represented in Fourier series coefficients, coupled to yield a large set of equations. These must be linearized and iteratively solved.
The HB method has appeared in APLAC since the early 1990s. Initially the implementation was of piece-wise type — the circuit was partitioned into linear and nonlinear sections, with the linear section presented as a Norton equivalent, and solved internally with linear methods. This approach is attractive when the number of nonlinear elements is small. At the end of the ’90s, a nodal harmonic balance analysis was implemented whereby the circuit was not divided into two parts, but all nodes fully treated to contain all harmonic frequencies. This approach is very fast for IC circuits consisting mostly of nonlinear elements, FETs and BJTs. It has been the basis for the APLAC RFIC simulation engine, and improved in every release since introduction.
Recent focus, however, has turned to the sampling of the Fourier coefficients, based on the notion that HB sampling is not only a computational procedure, but also a way of writing the harmonic balance equations in the case of nonlinearities. In a multi-tone excitation, it is possible to arrive at one-dimensional mapping of the multidimensional frequency indices representing the mixing products, and then use the fast Fourier transform. This leads to a very efficient algorithm.
Common methods of speeding calculation performance like multi-processor threading can readily be used with HB, because major computational efforts, matrix conversion and computation of the nonlinear voltage-controlled current sources can be directly partitioned among several processors sharing the same memory space. As has been mentioned, HB analysis featuring a very fast parallel scheme will appear in the next APLAC release. Early tests have shown simulation times to drop at least by one third for test cases including more than one thousand transistors.
The Final Product
Digital design has long dictated the structure of EDA environments. For the RFIC designer, however, the ability to incorporate algorithms of proprietary simulators into the design flow — whether at the IC level, board level or mixed — has yet to be realized. APLAC is committed to changing this situation in order to clear the path to speeding up the design process and improving the final result. For this new release the device-under-test (DUT) approach (see Figure 1) has been implemented into APLAC Editor to allow the use of the robust and fast RFIC simulation algorithms within Cadence and Mentor full custom design flows (see Figure 2).
This approach will give the following benefits for users: rapid characterization of systems, top-down approach from system level to modular circuit level and multi-level simulations (linear frequency domain, DC operation point, time domain, harmonic balance, phase noise, linear/nonlinear noise, temperature, etc.). All the algorithms support accurate yield predictions (Monte Carlo) and optimization for any component values in the circuit. Models are verified to vendor processes and provide reliable simulations. To utilize this link all that is needed is to define the Cadence or Mentor element property mapping for APLAC components using APLAC Editor’s mapping utility tool. After the correct process library and mapping definitions are in place the user can include Cadence and/or Mentor schematics just by adding hierarchical symbols for them.
To illustrate the efficiency and performance of the harmonic balance algorithm improvements, a 2.4 GHz QPSK modulator and demodulator circuit, designed using Cadence full custom IC design tools, was studied. This circuit is implemented on a 0.35 µm TSMC-compatible CMOS process, including 189 BSIM3 transistors and +100 passives (resistors, capacitors, inductors). Below the whole design is studied in detail and simulations are done using APLAC Editor’s Cadence link. Benchmark simulations are executed only for the highest hierarchy level but all modules can be analyzed using the same approach.
Figure 3 includes the following items for the modulator starting from left to right:
- The input signals: local oscillator differential signals, differential I and Q signals
- The local oscillator signal is fed to a polyphase filter, which makes a 90° phase shift
- After the polyphase filter the I and Q signals are up converted from 10 MHz to 2.45 GHz
- Then the RF signal is created first converting the differential signal to single ended and summarized
The demodulator portion includes the following items from left to right:
- The VCO that generates a 2.44 GHz reference signal
- The polyphase filter for 90° phase shift
- Then the RF signal is converted to differential and fed to the down converter mixer with local oscillator differential signals. Conversion is done using a Gilbert mixer from 2.45 GHz to 10 MHz
- The last steps in the receiver signal flow are the I and Q differential-to-single conversion with operational transconductance amplifier (OTA) based differential amplifiers and filtering with sixth-order active Bessel low pass filters
There is a biasing block above the receiver chain, providing DC currents for complete design. This circuit is analyzed using the new harmonic balance algorithm without the multi-processor option. All simulations have been done using an IBM Thinkpad T41 laptop with 1.4 GHz Intel Centrino processor and 512 Mbytes of RAM. First, the transceiver was analyzed using two-tone HB with mixing products up to the eighth order, resulting in 72 harmonic frequencies in analysis. Note that the VCO is also included in the analysis. In APLAC the oscillator analysis can be done first and the resulting oscillator steady-state signal used as an internal excitation for the oscillator. By doing this the VCO can be part of the whole chip analysis. Figure 4 shows the RF signal spectrum after the modulator, while Figure 5 shows the demodulator’s baseband I and Q signals without filtering and after active filtering.
Simulation time for this HB analysis was 40 seconds and the maximum amount of memory used during the analysis was 220 Mbytes. It was also verified that having multiple HB analysis only increases the simulation time linearly. This same HB analysis with the temperature loop from 10° to 30°C with ten temperature points took 6 minutes and 31 seconds, illustrating that HB analysis is extremely suitable for optimization and Monte Carlo analysis when large circuits are considered.
Implementing a multi-processor version using the threading scheme has produced the APLAC Harmonic Balance (HB) algorithm, which minimizes the memory requirement and simulation time, while maintaining accuracy. Computational effort with the newly implemented one-dimensional Fast Fourier Transformation (FFT) algorithm scales linearly with the number of analysis frequencies, while conventional methods require effort squarely proportional to the number of frequencies. Versatility enables the user to optimize any simulation result, with any number of variables, and enables a full multi-tone harmonic balance simulation of circuits with hundreds of transistors on a laptop in minutes, if not seconds.