The In-Phase and Quadrature Modulator (IQ Modulator) is a key component in modern wireless transmitters. It provides a convenient method for modulating data bits or symbols onto an RF carrier. IQ up-conversion has become the architecture of choice for implementing transmitter signal chains for end applications such as cellular, WiMax and wireless point-to-point. IQ modulators, however, can degrade signal fidelity in ways that are somewhat unique. These effects can degrade the quality of the transmitted signal during the modulation process, resulting in degraded Error Vector Magnitude (EVM) at the receiver which in turn degrades Bit Error Rate (BER). Fortunately algorithms exist that can correct for these imperfections.

This article will begin by describing a typical Zero-IF or direct-conversion transmitter along with providing a brief introduction to digital modulation. The imperfections introduced by the modulator will be examined with particular focus on the effect of temperature and frequency changes. In-Factory and In-Field algorithms that can reduce the effect of these modulator imperfections will also be discussed. Particular focus will be placed on the efficacy of In-Factory “set-and-forget” algorithms.

A Typical Wireless Transmitter
Figure 1 shows a block diagram of a direct-conversion wireless transmitter that uses an IQ Modulator to modulate a bit stream onto a carrier. A single bit stream is split into two parallel bit streams at half the original data rate. In order to limit the spectral bandwidth of the final carrier, the two bit streams are low-pass filtered in the digital domain (in order to do this, the original bit-streams must be digitally oversampled by the digital signal processor or Field Programmable Gate Array (FPGA). So, instead of a two bit streams, we now have two streams of digital words. The chosen resolution of these words will depend upon multiple factors such as the required signal-to-noise ratio of the link and the chosen modulation scheme (QPSK in this case). Commonly, word widths of between 12- and 16 bits are chosen.