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HRL Laboratories LLC announced it received a Phase II, 18-month contract from the Defense Advanced Research Projects Agency (DARPA) to continue its groundbreaking work on the COSMOS program, or COmpound Semiconductor Materials on Silicon.
The goal of the DARPA/Air Force Research Laboratory program is to develop new methods to tightly integrate compound semiconductor technologies with state-of-the-art CMOS (complimentary metal-oxide semiconductor) circuits in order to achieve unprecedented levels of circuit performance. The program targets high-dynamic-range (16 bits), high bandwidth (500 MHz), analog-to-digital conversion for challenging RF receiver applications, such as communications, radar and sensor systems.
HRL announced in December 2008 at the IEEE’s International Electron Device Meeting in San Francisco, CA, that it had successfully integrated silicon CMOS with indium phosphide (InP) double heterojunction bipolar transistors (DHBT), a major breakthrough in the HRL effort, which began in 2007 with an initial Phase I DARPA contract. The Phase I goal was to develop and demonstrate a viable process to integrate these two disparate materials, which when combined effectively, dramatically improve linearity, dynamic range and bandwidth, according to HRL’s COSMOS Program Manager Ken Elliot.
“The new HRL technology also offers outstanding overlay accuracy, solves thermal expansion and stress issues, and maximizes connectivity between CMOS and InP transistors," Elliott said. “No electrical degradation of the CMOS or InP HBT devices has been observed.”
In addition, the integration process is fully compatible with the device and interconnect scaling needed for future technology generations, with the added benefits of a less costly growth path and shorter time to market than potential alternative technologies.
The HRL technology may also represent the beginning of a paradigm shift for other materials and devices that could offer benefits if integrated with CMOS. For example, HRL’s COSMOS technology will enable advanced systems-on-a-chip and emerging technologies with a more rapid development cycle. This innovation will result in higher bandwidth and lower distortion signals for optical and RF communications.
Phase II of the program will focus on significantly improving both the yield and density of the heterogeneous interconnect process using the HRL 400 GHz, 250 nm InP HBT process combined with commercial 130 nm CMOS. The program has a target of producing a 500 MHz bandwidth digital-to-analog converter with 13-bit dynamic range at the rated bandwidth.