Executive Interview: Chuck Fox, Jazz Semiconductor
Chuck Fox – Vice President of Sales and Marketing at Jazz Semiconductor spoke with Microwave Journal editor, David Vye about the new .18um CMOS process, the Analog-Intensive Mixed-Signal Initiative and how their latest Silicon technology is ready to deliver the single chip radio. Appointed Vice President of Sales and Marketing in July 2007, Mr. Fox has over 25 years of experience in the semiconductor industry providing executive leadership with strategic, operational and marketing responsibilities. Previously, he was CEO of KeyEye Communications, a fabless analog-intensive mixed-signal semiconductor company. He also served as President and CEO of Chameleon Systems, a high-performance DSP processor company and Vice President of Marketing for Cradle Technologies, a multi-processor DSP chip company.
Mr. Fox was instrumental at Xilinx in growing it from a small private company into a multi-billion dollar, FPGA industry-leader both as Vice President of Worldwide Marketing and as Division General Manager. He also spent 10 years in various management positions at Intel. Mr. Fox earned both BSEE and MBA degrees with honors from the University of Wisconsin, Madison and completed the AEA Executive program at Stanford University.
MWJ – Chuck, thanks for taking the time to speak with us today. There seems to be a lot of activity going on at Jazz Semiconductor. Your company has announced the Analog-Intensive Mixed-Signal (AIMS) Initiative along with news that its .18um CMOS process is available for complete radio integration. The two JAZZ white papers entitled: “SiGe HBT Amplifiers Replace GaAs for Wireless and Broadband applications (Silicon Radio Platform)” and “Analog-Intensive Mixed-Signal Solutions” and the article in this month’s Microwave Journal “Design Enablement for RF and Microwave IC Design” describe the process technology and support that will lead to the next level of wireless device integration, namely a single chip radio that combines the transceiver/receiver and power management with the power amp and antenna switch. Before we get to the single chip radio, I’d like to talk about SiGe HBT power amplifiers. Due to performance needs, the PA has been the last bastion for III-IV semiconductors (i.e. GaAs, AlGaAs, InGaP, etc.) in the handset. The SiGe HBT white paper discusses the viability of replacing GaAs power amplifiers with devices based on your .18um SiGe HBTs. How does a SiGe HBT amplifier from your .18um process compare to best-in-class GaAs devices in terms of linearity and efficiency for today’s 3G handsets?
CF – We have data on the driver stage with WCDMA modulation applied that indicates our SiGe 0.18 is equivalent (or better) to GaAs in terms of the linearity vs. efficiency. Jazz is optimizing our large power devices to provide the appropriate linear power (28 dBm). Combined with the driver, it is expected to yield typical linearity of 38dbc with PAE of ~40%.
MWJ – Are there other performance or operational (i.e. biasing) advantages of SiGe HBT power amplifiers over GaAs that you feel are worth mentioning?
CF – The known advantage of silicon over GaAs is thermal conductivity. This allows the design of compact power cells without the downside of thermal degradation. The other advantage is the ability to integrate functions such as power control and programmable logic that otherwise is difficult in GaAs. At low power, SiGe HBTs typically have an advantage in terms of linearity versus power added efficiency when compared to GaAs InGap.
MWJ – Could you describe how the relatively new .18um process enhances the active device performance?
CF – We have enhanced our standard SiGe and CMOS devices by increasing their operating voltage range making them rugged for power amplifier applications. This only minimally impacts performance (particularly for the SiGe device) making them quite efficient for these applications. We have also created a process by which these devices can be integrated on the same wafer as an SOI antenna switch.
MWJ – The behavior of on-chip passives (i.e. inductors) also plays a big role in circuit performance. Passives are notoriously lossy on Silicon; you are reporting inductors with Q’s between 18 and 25. Is this performance the result of your “High Q” option? Could you tell us more about the technology behind the better performance?
CF – Jazz has developed a unique design enablement tool called the Jazz Inductor Toolbox (JIT), which optimizes the performance of inductors. Jazz has extensive experience on inductor models and with volume fabrication. Also, one of the features that improves “Q” as well as broad banding the inductors is the availability of shielding under the inductors.
MWJ – The cost savings of SiGe devices are related to the availability of 8-inch wafers versus 6-inch wafers for GaAs, allowing twice the number of devices to be fabricated per run. How does the price of a SiGe PA compare to a similar GaAs device?
CF – The merchant market foundry wafer price for a 6” GaAs wafer is in the same range as the merchant market foundry wafer price for an 8” SiGe wafer. Therefore the die cost of a SiGe PA would be about 50% of a similar GaAs device. Over time, the SiGe wafer price will continue to decline since it is based on silicon and can take advantage of other wafer volume demand with many other applications for the SiGe wafers. Therefore, the die cost of a SiGe PA will continue to decrease faster than the equivalent GaAs device.
MWJ – According to the report by Strategic Analytics that was presented at this year’s European Microwave Week, silicon mask sets cost between $50K to $330k (can be > $1M) versus $30k to $50K typical for GaAs. I assume the upper range for the silicon reflects highly complex ICs and that the cost of masks for SiGe PA devices is somewhat comparable to GaAs. Is this assumption correct or are SiGe power amps more costly to design? Is it a straightforward calculation to determine the volume of devices necessary for the production-run savings to offset any additional design costs or do many factors play into determining the ROI of SiGe versus GaAs?
CF – Silicon mask set costs depend primarily on the smallest feature size of the silicon process node and the number of masks required. The most advanced smallest nodes of 65nm have mask sets that approach $1M. The SiGe PA devices are made using CMOS transistor nodes that are much larger - usually 350nm or 180nm. These mask set costs range from $60K to $250K depending on process node and number of masks. GaAs PAs do use older larger transistor nodes and have fewer mask steps so their total mask costs can be significantly lower than a SiGe PA. On a strictly die cost basis, the production volumes needed for a SiGe PA offset the increased mask costs. However, silicon based PAs have the advantage in that other CMOS based analog functions (such as controllers, power management, switches, filters and even the transceiver) can be integrated on the PA die to increase the analog functional density. This reduces the overall system cost and board space and increases system reliability.
MWJ – What is the current ratio of Silicon/SiGe to GaAs components in the RF Bill of Materials (BOM) in a typical handset and what does the historical trend predict the ratio will be in the next few years?
CF – This ratio varies widely per chipset (transceiver) solution and the particular handset so I cannot give you a specific ratio. However, we expect that SiGe PAs will displace GaAs amplifiers in cost sensitive as well as lower power and linear applications. The adoption is most likely in 3G UMTS handsets where the number of amplifiers is higher.
MWJ – Given silicon’s low cost advantage for high-volumes, which wireless radio markets are best poised for SiGe HBTs to displace GaAs devices? Are there any GaAs-free wireless radios in the market today?
CF – The first markets where SiGe HBTs are being used to displace GaAs devices are in Wireless LAN and WiMAX power amplifiers. These applications have lower power requirements for the amplifier and hence it is easier for the silicon based PA devices to meet those performance requirements. Also, those WiLAN/WiMAX applications that integrate many different radios such as Bluetooth, GPS, and multiple WiLAN standards need multiple PAs. These multi-radio applications can more easily benefit from the space and cost benefits of silicon integration using SiGe.
MWJ – Replacing the GaAs PA with SiGe HBT is certainly a key step toward achieving the single chip radio. Is this one of the more compelling arguments for using a SiGe HBT power amplifier - its ability to be integrated with other CMOS technologies?
CF – When the SiGe HBT power amplifier can meet the specific performance requirements of the application, then cost benefits of the silicon approach can be up to 50% depending on the volume. However, the integration with other CMOS technologies is also a significant motivation to use a SiGe HBT solution.
MWJ – What are the recommended Jazz SiGe process variants for designing handset amplifiers and how many metal layers are available?
CF – There are power amplifier variants that are available to suit particular applications or air interfaces. In addition, these are available in an SOI option as well, further enhancing the integration of the RF Switch into one die. Generally, the low cost power amplifier process uses three metal layers (e.g.SBC18 MW) although the total metal layers can be up to six.
MWJ – Why do design groups choose to use more top metal layers?
CF – Generally the top layer has the least resistance (sheet metal) and hence lower losses.
MWJ – More and more electronic devices need to support multiple air interfaces, which would seem to play well for technologies that promote integration. Is this a leading consideration for shifting to Jazz’s AIMS technology?
CF – Absolutely. The multiplicity of air interfaces (GSM, GPRS, EDGE, WCDMA, UMTS, cdma2000, PHS, etc) and the increase in protocols (cellular, 802.11x, WiMAX, GPS, UWB, Bluetooth, etc.) require designers to produce radios for all of these wireless interfaces. This requires a receiver/transceiver, a power amplifier, often an antenna switch and a host of control and power management functions. The ability to provide the designer with a rich set of integration options over cost, space, power and performance is the key element of the concept of increasing functional analog density in next generation wireless chips. Our AIMS technologies are ideally suited to meet this challenge.
MWJ – For a Silicon-based radio, are there standard PA cells available for integration? What can you tell us about these PA cells, their capabilities, the power ratings that are available and the foundry support that helps engineers adapt these cells for their own applications?
CF – Jazz offers a suite of PA cells available now in our PA Design Library (PADL) ranging up to 30dBm of output power. We will be releasing larger cells up to 34dBm in the near future. To help customers, we provide a design manual with load-pull, large signal characterization of each cell as well as expert applications engineering support.
MWJ – I’d like to talk about this integration, the process technology to support it and what Jazz is doing for design support. The Jazz “AIMS” white paper provides an introduction to the specialty CMOS technology modules that support the various silicon-based radio components and the baseline RF CMOS technology that supports integration of all these blocks into one chip. This paper also discusses a Silicon on Insulator (SOI) option that is available for integrating the PA and switch. What SOI method does Jazz use? What are the benefits of SOI technology relative to conventional bulk CMOS processing?
CF – SOI has the advantage over bulk that each device can be dielectrically isolated from the substrate and from other devices. This allows devices to "float" to high voltage levels without breaking down. This enables the integration of a switch, which must isolate high voltage levels from the rest of the system. Jazz has the unique capability of offering integrated PA cells built on the same SOI wafer used from the switch. This differs from other foundries where the PA process and the SOI-switch process are built on separate wafers types and thus cannot be integrated.
MWJ – Is the SOI option more expensive?
CF – Yes, the SOI option requires a different and much more expensive wafer substrate starting material from the substrate supplier. This can add several hundreds of dollars per wafer in additional cost. As the substrate suppliers move to 12” wafers to supply SOI to the high volume microprocessor vendors such as Intel and AMD, it is expected that the price of 8” SOI substrates will come down considerably.
MWJ – Are there currently single chip radios in development at Jazz? Any in production now?
CF – Yes, we know of a several 802.11a/b/g chips that are in production that include the transceiver, power amplifier, controller, and power management functions on a single chip. Additional designs are in process in the 802.11n and WiMAX areas.
MWJ – We hear a lot about time-to-market and time-to-revenue. I imagine most new designs don’t start from scratch and are actually evolutions of existing designs. Is this the case?
CF – Yes, this is often the case. We provide some common low level analog IP blocks. However, in the high-speed analog domain, most customers develop their own libraries that capture their IP in the form of specialized circuit design and physical layout. They use this internally developed IP to spin new designs to reduce time-to-market and increase the probability of first time success on a new analog chip design.
MWJ – If we were to consider the development of a next generation radio IC that was based on some “typical” mix of new design and re-usable IP, about how many engineers might one expect to find working on it and what would be a typical range of time–to-revenue?
CF – This would depend on the complexity and features of the radio IC. In addition, the expertise of the designer(s) comes into play as well. Jazz has placed considerable effort in minimizing the design cycle by modeling and characterizing its process technology and devices thus shortening the design cycle. Time-to-revenue can be from six to nine months depending on the number of passes.
MWJ – The article in Microwave Journal discusses the models, design tools and support that will allow engineers to expedite the design process successfully (what Jazz is calling “design enablement”). What are some of the more unique features of this design enablement compared to the “standard” process design kits offered by other foundries? Is Jazz attempting to bring best practices from the digital design realm into the RF world?
CF – Beyond the design kit, Jazz provides the customer’s designer a Power Amplifier Design Library (PADL), which contains data at the air interface specifications on different device sizes (p1db). This saves considerable time and eliminates certain design risks. The goal is to have the customer design new products and not to develop a wafer fabrication process.
MWJ – Jazz is a pure-play foundry. Do you maintain a design staff as part of your support organization? If so, what level of involvement is there between this group and your customers? Do they help with design issues or mostly help support design tools and answer process or modeling questions?
CF – Our AIMS strategy is based on the concept of both innovation in analog and mixed-signal process technologies as well as innovation in developing the design enablement solutions to speed our analog chip designers’ time-to-revenue. We have a unique desire and responsibility as a pure-play AIMS foundry to proactively speed our customers’ design cycles and reduce their chip iteration cycles. We do this via superior technical support of models and developing innovative design enablement tools. We also have a small design services staff and work closely with a variety of external high-speed analog design services companies knowledgeable about the Jazz methodology.
MWJ – Jazz recently held its annual technology conference, which was focused on AIMS foundry solutions. What can you tell us about this event?
Our 2nd annual technology symposium was held in early November at our Newport Beach headquarters and attendance was up 30% from last year. This one-day event featured a keynote speech by our CEO, a comprehensive market analysis presentation, a lively customer panel discussion, and a program of customer presented design success stories. In addition, Jazz R&D staff provided detailed technical presentations covering both our innovative AIMS process technologies and design enablement capabilities and tools. We also had 19 sponsors that set up exhibits and displayed their support services and products. Additionally, we provided tours of our Newport Beach 8” AIMS fabrication facility throughout the day. The feedback from customers on the new AIMS foundry focus and the innovation in technology and enablement was impressive. Planning for next year’s event is underway and is assured of being even bigger!
MWJ – Great information Chuck. You and your team have been very busy developing the technical innovations and support that the industry has been asking for over the past few years. I look forward to reading about the devices that your customers will be designing in the near future. Thanks again for your time.