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Industry News / Semiconductors / Integrated Circuits / Software & CAD

Agilent Releases SystemVue

May 3, 2011
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Agilent Technologies Inc. announced the release of SystemVue 2011.03, a leading system-level communications design environment. With this release, SystemVue now enables wireless system architects and system-on-chip designers to validate multiband, high-transistor-count wireless IC designs accurately against the latest communications standards.

Until now, wireless communications architects have lacked the accurate commercial modeling formats needed to qualify the system-level performance of their RF/analog and mixed-signal CMOS transceiver designs. Agilent’s GoldenGate and SystemVue environments now connect in two ways to help system-on-chip designers meet the challenging requirement of ETSI LTE/LTE-A and other emerging wireless standards, via an exclusive, fast circuit envelope (FCE) model or direct envelope-level cosimulation.

The new FCE models execute 1,000 to 100,000 times faster than the original RFIC physical designs, with virtually no loss in accuracy at the system level. Unlike indirect commercial modeling approaches, the new FCE models can account for nonlinear memory effects and are generated from the RFIC design itself, with little human intervention or coding. They can also account for frequency- and power-dependence, frequency translation, multiple ports and internal nodes, and can be exported at various settings of control states, bias voltages, process corners, temperatures and impedance loading.

The new FCE models run natively in SystemVue, as part of the W1719 RF System Design Kit. For challenges that require dynamic behaviors and the highest possible analog accuracy at the system level, a direct cosimulation mode is also available.

“Agilent’s new modeling technology breaks down design flow barriers for enterprise-level wireless IC designers,” said Paul Colestock, Product Manager for Agilent’s GoldenGate products. “With no programming, you can quickly verify a whole functional chain against instrument-grade reference IP using calibrated, bottom-up models that come out of your existing design flow.”


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