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EDA Focus: HSPICE Enhances Speed and Capacity

October 9, 2010
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Last month, Synopsys announced HSPICE® Precision Parallel (HPP) multi-threading technology would be a significant enhancement to the next release of the analog/mixed-signal circuit simulator HPICE 2010. The new capability, which utilizes a scalable multi-core engine, delivers up to 7X simulation speed-up for complex analog and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analog analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. The enhanced speed and capacity should allow design teams to accelerate verification of their analog circuits across process variation corners and reduce the risk of silicon respins.

Recent customer benchmarks show significant speed advantages using the new precision parallel multi-threading technology. For instance, a phase lock loop design consisting of over 7,000 transistor and RC components was solved in 12.5 hours compared to the 148 hours required by other simulators. A clock tree with over 10 million elements experienced a reduction in simulation time from 108 hours down to 7.7 hours and a sigma delta convertor that took 16 hours to solve in other simulators saw its simulation time cut by more than half. The company tested the enhanced convergence algorithm on more than 300 test cases including PLLs, DC-DC, A/D, D/A converters, and SERDES circuits. 95 % of these circuit converged without user intervention, the rest were solved with simple command options set be the user.

New built-in features include loop stability analysis for understanding frequency domain loop and phase characterization, transient noise analysis using Monte Carlo and Stochastic Differential Equation methods, High frequency analysis supporting frequency and time domain phase noise and jitter analyses; and StatEye, which supports fast statistical eye diagrams with orders of magnitude speed improvements over traditional simulation.

HSPICE Precision Parallel Technology

In 2008, HSPICE was one of the first commercial circuit simulators to introduce full multi-threading capability. The new HPP technology takes multi-threading performance to a new level for complex analog circuits with significantly faster speed and class-leading multicore scalability. HPP combines an adaptive sub-matrix technology with optimized cache utilization and streamlined device model evaluation to obtain fast, highly-scalable performance on today’s multicore machines. Efficient memory management allows simulation of post-layout circuits larger than 10 million elements.

“We evaluated HSPICE Precision Parallel technology to speed up our multimillion-element complex clock mesh network simulation,” said Antonio Todesco, SMTS design engineer, Graphics Silicon Engineering group at Advanced Micro Devices. “HSPICE Precision Parallel technology allowed us to achieve one-day turnaround time for ECO, extraction and simulation while using less memory and delivered the timing resolution needed to support clock mesh circuit integrity.”

Availability

The HSPICE Precision Parallel technology is in limited customer availability and will be generally available in the December 2010 release. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

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