SEMI, a global industry association that unites the entire electronics manufacturing and design supply chain, and the UCLA Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS) announced that they have won a $300,000 grant from the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST) to produce a roadmap for advancing heterogeneous integration and advanced packaging technologies in the U.S.  

The roadmap will build upon the International Technology Roadmap for Semiconductors (ITRS) and Heterogeneous Integration Roadmap (HIR) by translating the HIR into a blueprint that defines requirements for rolling out the roadmap in U.S. semiconductor factories. The grant, one of the first awarded by NIST's Advanced Manufacturing Technology Roadmap Program (MfgTech), will fund the project for 18 months. 

Supported by microelectronics leaders, SEMI and UCLA CHIPS will create a technology-neutral communications platform for peers across the supply chain, academics and industry experts. SEMI will also define a process for prioritizing and guiding critical areas of the HIR to standardization, while UCLA will organize academically themed workshops and panels to ensure the roadmaps are scalable and extendible as new applications evolve and new processes are developed. 

“While the Heterogeneous Integration Roadmap is application-focused, our work will translate this roadmap into a manufacturing infrastructure blueprint that starts at the basic materials used in advanced packaging and breaks down integrated processes into individual unit processes,” said Dr. Subramanian Iyer, distinguished professor of electrical and computer engineering and director of UCLA CHIPS, which is housed at the UCLA Samueli School of Engineering. “Some of them will diverge from traditional Si processes and include custom manufacturing tools and processes that address dies, wafers and panels. Our roadmap will also be customizable to work with many application-dependent variables."

“SEMI and UCLA CHIPS look forward to leveraging our expertise in semiconductor and packaging roadmaps—from upstream innovations to downstream manufacturing infrastructure—to develop the HIR and take the next step toward factory implementation,” said CTO and Vice President of SEMI Technology Communities, Dr. Melissa Grupen-Shemansky, SEMI. “SEMI will also turn to its workforce development strategies to offer heterogeneous integration technology training at all levels of education to meet the growing need for advanced packaging talent in the U.S.”