For smartphones, new technologies like 5G provide faster access to the internet while on the move, as well as more bandwidth, smaller form factors and longer battery life. To give consumers more goodies, designers must integrate more functionality into their products. In many applications, this problem is solved by using higher levels of integration, that is, using SoC design to achieve higher performance. Unfortunately, it is difficult to realize 5G systems just using SoC designs. To achieve the levels of performance required for 5G designs, heterogeneous designs that integrate multiple technologies—such as silicon, GaAs, GaN—are needed.

Looking at the evolution of cell phone technologies over the long durée, we can see the trend from board-level products realized with discrete components to highly integrated products using SoC and RF modules (see Figure 1). This product evolution requires significant changes in the design methodology. In early designs, the designers could focus on RF block-level design because system-level integration was performed at the board-level of the design. However, when designing for 5G, the level of integration and the complexity of the functionality means that designers need to up their games—the effort required to verify their designs has increased significantly.



Figure 1: Evolution of design effort over cell phone generations.

The challenge is how to perform complete design verification without impacting time to market. Digital designers have evolved sophisticated methodologies that enable comprehensive verification of their designs without clobbering the time to market for their products. Sadly, until cell-based design has been enabled for custom IC design, this methodology to reduce verification time can’t be applied directly to the mixed-signal and RF components in a design. Luckily, this methodology can be adapted for mixed-signal and RF design in three steps:

  1. Perform system-level simulation. To identify issues as early in the design process as possible, we need to move the system-level measurements into the IC design environment, making 5G sources available to RFIC designers to enable verification.
  2. Automate RF verification. Automation has been used extensively by digital designers to overcome the challenges of design verification. We can borrow this concept, enabling the methodology by building on the existing capabilities of the Virtuoso ADE Product Suite. Since most designers are experienced with this product, this minimizes the learning curve.
  3. Automate RF regression testing. Verification planning is a systematic approach for defining what needs to be verified and how to verify it.

Performing System-Level Simulation

Traditionally, RF designers must export their designs to system-level simulators since complex stimulus is required to verify system-level compliance. Even if the stimulus can be imported from the system-level simulator to perform envelope-following analysis, it is a herculean task to set up the simulation to achieve the high accuracy needed for system-level simulation. This approach to verification of passing the problem “over the wall” is known to cause issues, as it is highly dependent on good communications between the parties to achieve design closure.

An alternative approach would be to verify that a design is compliant to standards as part of the block-level verification process. However, for circuit designers to perform system-level simulations, a change in the use model is required. A designer usually sets up the testbench to characterize the design (see Figure 2). Now, designers must understand the system-level measurements to set up the simulations, which can be challenging. The solution is to change the use model so that designers define the measurement they want to perform instead of setting up simulations.

Figure 2: 5G NR wireless testbench for a power amplifier.

By allowing designers to focus on the measurement they want to perform, such as selecting the channel number or modulation type, productivity can be significantly improved. Once the measurement is defined, the simulation can be set up automatically to optimize the accuracy. Designers need to perform multiple measurements, including error vector magnitude (EVM), bit error rate, and adjacent channel power ratio (ACPR). Another challenge: performing system-level simulations at the transistor level can be time consuming. As a result, the solution must include the ability to perform fast envelope analysis, which was developed to accelerate system-level simulation time. With fast envelope analysis, designers can confirm that their designs are compliant to standards in a reasonable time. Figure 3 shows the constellation plot used to calculate the EVM and the spectrum with the spectral mask used to calculate ACPR.


Figure 3: Results of system-level simulation

To summarize this first step, circuit designers test designs for compliance to standards using existing design tools. The result is less effort for system-level verification since the design is correct by construction.

Automating RF Verification

Step two of the methodology is to gather all the tests required to assure compliance so they can be run. Previously, designers would perform this task manually, then compile the results into spreadsheets. This manual process requires significant effort from the designer to maintain the spreadsheet throughout the project. Since the data entry is manual, it is prone to error when generating the document for process corners, across operating modes, etc. If this methodology is performed manually, there is significant risk to both the product development time and potential design issues being missed by the verification. Compared to digital design verification, where there are daily regression runs, this approach to design verification is problematic.

Once automated, the tool then can be used to manage the verification. All the individual tests being performed are gathered into a single regression test for the block. Each measurement includes a specification, the measurement value after the simulation and a judgment whether the result passes or fails—that is, if the measurement is compliant.

For example, there might be separate testbenches for the power dissipation in different modes in addition to the system-level measurements. All the tests required can be captured in a single cell view (see Figure 4). The box highlighted in red shows another useful feature for automating verification across multiple modes of operation, which is often needed. In the figure, the performance with different modulations is being tested.


 Figure 4: Power amplifier verification.

However, simulating and verifying blocks is useful but not sufficient. Designers need a simulation controller to automate the regression test of their designs once the verification test has been defined.

To summarize, by collecting the wireless testbenches to create automated regression tests for a design, designers can perform daily regression tests to assure the blocks will meet the system-level requirements without impacting the design schedule. The designer can click a button to kick off the regression test and come back when it is complete, to check the results and minimize the impact of verification on time to market.

Automating RF Regression Testing

The final step in this methodology is verification planning. In step two, we looked at how the verification process could be automated; in this step, we look at how to map the system-level designer’s requirement for a block to the verification test.

Using the system-level requirements to drive the verification means nothing is missing in the verification test. Figure 5 shows how the system-level requirements can be mapped to the verification tests discussed previously. The left panel captures the requirements from the system-level designers, and the right panel describes the implementation and the tests to verify each of the requirements. Sometime, one requirement can require multiple tests to verify. Up to this point, we have been discussing verification of a single block; however, real designs have many blocks.


Figure 5: Power amplifier regression testing.

Figure 6 provides a cell view showing a transmitter chain including a power amplifier, the power amplifier integrated into a balanced amplifier and other blocks such as an up-converter and the baseband digital-to-analog converter used to generate the transmission signals. For each system-level requirement, testbenches are required for the mapping, shown by the green chain link. Mapping assures no holes in the regression test used for verification.


Figure 6: RF transceiver showing testbench mapping.

Once the regression suite has been created, the next step is to automate the regression process. While this example shows a system-level verification of an RF transmitter, the basic methodology is generic. For example, the requirements could be from a product datasheet for a design. The solution also supports automating the regression suite, since running the test is as easy as pushing a button.


To summarize, just verifying a parameter is not enough. Designers need to be able to plan, that is, link from the system-level requirements to the various testbenches designers create to verify the design is compliant with the standard it must support. These simulations can be automated, enabling regular regression runs to be performed.