PA Forum 2020

November 17, 2020

Don’t miss this one-day online Power Amplifier Design Forum featuring industry leaders covering key design topics for RF design engineers.

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Keynote: Class-F PA Design Based on a New Analytical Formulation
Dr. Steve C. Cripps, Cardiff University

CrippsClass-F power amplifier (PA) design has traditionally involved terminating even harmonics with a short circuit and odd harmonics with an open circuit. In practice, this is impossible to achieve over any useful bandwidth as it is based on idealized assumptions that lead to an intractable solution, whereby the third harmonic voltage amplitude is zero divided by zero. This presentation puts the Class-F mode analysis back into the tractable world, mainly through the inclusion of a novel but realistic model for the I-V knee region of the device. This results in a set of equations that can be solved, leading to useful practical design guidelines. In particular it is shown that the requirement for an open circuited third harmonic can be substantially relaxed with only minor reduction in efficiency.

Designing a Broadband GaN Power Amplifier Covering 400-3000 MHz For Saturated Applications
Jack Brunning, Ampleon

BrunningThis presentation demonstrates a design approach for a broadband saturated amplifier used in continuous wave (CW) saturated mode. In particular, the design uses a 25W discrete gallium nitride (GaN) on silicon carbide (SiC) high-electron-mobility transistor (HEMT) and is required to provide a minimum of 42dBm output power at 40% drain efficiency over a fractional bandwidth of 153% using planar matching. An integrated co-simulation approach incorporating load pull for optimal impedance extraction, network synthesis, and electromagnetic (EM) analysis is employed that utilizes a methodology developed with the Cadence® AWR Design Environment® platform to produce a first-pass reference design. The design flow demonstrated uses the device nonlinear GaN HEMT model, ATC capacitor models, and AWR® Microwave Office® circuit design software, including EM analysis and layout.

Effect of Load Mismatch on Power Amplifier Performance
Dr. Dominic FitzPatrick, AMETEK-CTS

FitzpatrickPower amplifier (PA) characteristics are typically measured in a 50Ω environment. While some datasheets state “stability into open and short circuit loads,” others note “operation at full power” into open and short circuits. It grows even more confusing with statements like “operation into all loads” without defining what “operation” means or noting that this includes a technique often referred to as “fold-back,” (where the amplifier gain is reduced above a certain reflected power level). This presentation will discuss why these different statements are made and what happens inside a PA under mismatched loads. Using measurements and simulations a better understanding of the real performance will be gained.

Modelithics Modeled Qorvo QPD1009 Power Amplifier Design
Chris DeMartino, Modelithics and Benny Haddad, Cadence

DemartinoThis presentation demonstrates the design of a power amplifier (PA) with a Modelithics® model for Qorvo QPD1009 gallium nitride (GaN) field effect transistor (FET) using the Cadence® AWR Design Environment® platform. The core circuit design uses the latest load-pull technology in the software, the transmission line effects are simulated using the integrated planar EM solver and the source matching circuits are created and optimized using the network synthesis wizard.

Loop Gain Envelope Stability Analysis of MMIC Power Amplifiers
Dr. Michael Roberg, Qorvo

RobergLoop gain analysis is typically performed on RF/microwave power amplifiers in order to ensure that stability is achieved for a wide range of applications from low frequency up to frequencies where device oscillation is no longer possible. Rather than evaluating the loop gain for all combinations of input and output reflection coefficient phases, a new loop gain envelope technique has been shown to cut the simulation time from hours down to seconds, making it ideal for stability optimization. This talk presents a method for evaluation of the loop gain envelope, as introduced recently within the V15 release of the Cadence® AWR Design Environment® platform, using a MMIC amplifier as an example.

Load-Pull Based Design Flows for High Power Amplifiers
Chris Bean, Cadence

BeanThis presentation showcases the advanced load-pull technology in the Cadence® AWR Design Environment® platform for high-power amplifier (HPA) designers who must meet aggressive performance targets in short design cycle windows. Measurement techniques for load pull, source pull, harmonic load pull, and baseband load pull will be discussed. Specific new features in the latest release of the software for PA design will also be highlighted, including data management enhancements, ease-of-use improvements, as well as automated matching network synthesis, which integrates seamlessly with load-pull measurements to ensure that the best possible PA performance is achieved.

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