Doherty power amplifiers (PA) are widely used below 6 GHz to improve power-added efficiency (PAE) for communications applications. Although the benefits of the Doherty architecture are compelling, the challenges of designing Doherty PAs increase as the frequency of operation moves toward mmWave. LDMOS, which is commonly used in discrete form below 6 GHz, has limited performance and more integrated approaches are needed to minimize parasitic inductances and capacitances. GaN technology offers significant performance advantages for realizing RF/microwave PAs. More recently, short gate length GaN on SiC MMIC processes have become commercially available, offering the possibility of designing high efficiency Doherty PAs at mmWave frequencies. This article will describe the design of a Doherty PA MMIC for the 5G frequency band at 28 GHz. First-pass design success was achieved using an asymmetric topology fabricated on the commercial 0.15 μm G28v5 GaN on SiC foundry process from Wolfspeed. The MMIC was assembled in a cost-effective, compact 4 mm x 4 mm QFN package. Details of the design, simulation, layout and packaging will be discussed.
As GaN on SiC technology advances, new possibilities for PAs emerge. GaN on SiC has been successfully used at sub-6 GHz and to Ku-Band frequencies, but the source-coupled field plates often used to enhance breakdown voltage and increase power density have limited the maximum operating frequency of GaN transistors. Competing technologies such as GaAs and SiGe achieve higher operating frequencies with similar geometries, and these have become preferred high performance semiconductor technologies at mmWave. However, GaN on SiC processes with gate lengths of 0.15 μm are now available through foundries, with attractive performance at mmWave. This means the advantages of GaN on SiC - high power density, higher output impedance and lower I2R losses - can be realized in the 28 GHz 5G band.
PRFI has designed GaN PAs using both discrete devices and as custom MMICs, including a GaN on SiC Doherty PA for the 3.5 GHz 5G band.1 This, combined with the company’s experience with mmWave PAs and front-end modules in various GaAs technologies, has been used to extend the Doherty amplifier to mmWave.2,3
DOHERTY PAS
Figure 1 Doherty amplifier architecture.
The Doherty amplifier configuration (see Figure 1) comprises a main or carrier amplifier, biased in class AB, and a parallel auxiliary or peaking amplifier, biased in class C. The improvement in PA efficiency stems from the complementary operation of the main and auxiliary amplifiers: when the PA is operating at moderate power levels, only the main amplifier is active, which reduces DC power consumption. With high level input signals, the auxiliary amplifier begins to amplify, boosting the output power capability of the PA.
The output matching network of the Doherty PA consists of two impedance transformers: an impedance inverter and a common matching network. Together, they present optimal impedances to the amplifiers in both compressed and backed-off operation. The impedance inverter at the output of the main amplifier provides a 90 degree phase shift between the main and auxiliary amplifier paths. In large-signal operation, to ensure the outputs from the main and auxiliary PAs are combined in phase, a 90 degree phase shift is added to the input of the auxiliary amplifier.
Compared to sub-6 GHz Doherty amplifiers, mmWave PAs add several design challenges. Transmission line and matching element losses are higher, and the transistors have lower transconductance, so gain is more difficult to achieve. Also, parasitic capacitances and inductances have more effect at mmWave frequencies, making it more difficult to present a real impedance (ROPT in Figure 1) to the main transistor output.
GaN PROCESS
This PA design uses GaN devices fabricated on Wolfspeed’s G28v5 GaN on SiC process. The transistors have 0.15 μm gate length, operate at a bias voltage of 28 V and have a breakdown voltage greater than 84 V. The devices achieve a power density of 3.75 W/mm, compared to less than 1 W/mm for a typical high power mmWave GaAs PHEMT process.4 While most GaN on SiC processes have a substrate thickness of 100 μm (4 mils), the G28v5 substrate thickness is 75 μm (3 mils), which improves high frequency operation. A variety of transistor layouts are available in the process design kit (PDK), including intra-source and edge via layouts. The gate and drain finger spacing of the FETs can be modified to trade off the thermal resistance, high frequency operation and die area. Self-heating models in the PDK enable designers to predict the operating channel temperatures inside the transistor.
For Doherty amplifiers, GaN on SiC is preferred over GaN on Si for two reasons: the thermal conductivity of SiC is around 3x better than Si, improving the heat transfer from the die, which lowers channel temperature and improves reliability. SiC has less RF loss, so the auxiliary amplifier branch presents a high impedance when pinched off. This avoids loading the main amplifier, yielding better back-off efficiency.
PA DESIGN
An asymmetric topology was selected for the Doherty PA design to achieve better efficiency at higher back-off powers. Theoretically, a symmetric Doherty PA has a peak efficiency at 6 dB back-off, where an asymmetric Doherty with a 2:1 gate width ratio between the auxiliary and main branches achieves peak efficiency at 9.5 dB back-off. Actual device knee voltages reduce the available voltage swing, so peaks at 8 dB back-off are usual. This is compatible with modulated communications signals, which typically have peak-to-average power ratios of 8 to 10 dB. While an asymmetric configuration has performance advantages over a symmetric design, it requires considerably more design effort. Two separate PAs must be designed and then integrated into the Doherty topology. The phase and amplitude responses must be engineered to ensure the powers from the main and auxiliary branches combine in phase at the output.
Figure 2 28 GHz Doherty amplifier die.
The asymmetric Doherty PA is shown in Figure 2. The main amplifier is at the top and the auxiliary amplifier, with its larger gate width, is at the bottom. Designed to be compact enough to be assembled in a 4 mm x 4 mm QFN package, the die size is 2.40 mm long x 2.15 mm wide.
The input split and 90 degree phase shift use a Lange coupler, which was electromagnetic (EM) simulated for maximum accuracy. The spacing between the Lange coupler fingers determines the coupling, hence the power split between main and auxiliary branches. The 50 Ω terminating resistor on the isolated port of the Lange coupler was sized to dissipate the expected power reflecting into it.
