Cobham Advanced Electronic Solutions announced today that it has introduced two new offerings to its Cobham Gaisler family of Open Source IP Cores. The new LEON5 IP core implements the SPARC V8 32-bit Instruction Set Architecture (ISA), a 32-bit architecture. Based on VHDL, Cobham’s LEON5 super-scalar dual-issue processor provides software backward compatibility with previous generation LEON processors, while increasing performance both in terms of maximum achievable operating frequency and amount of computations performed per system clock cycle. Cobham’s new NOEL-V supports RISC-V, an open, free ISA that enables a new era of processor innovation through open standard collaboration. Cobham, a Gold-Level Member of the RISC-V Foundation, plans to introduce a wide range of RISC-V offerings. NOEL-V, Cobham’s initial RISC-V solution, is a RV64GC compliant processor Intellectual Property (IP) core, a 64-bit architecture, written in VHDL. Both of Cobham’s new Processor IP Cores will be available for initial download into Xilinx UltraSCALE FPGAs.
Cobham is a world leading supplier of advanced processor products, providing them both as fault-tolerant IP cores for integration into custom microelectronics, and as radiation-hardened high-reliability components for the space market. Cobham also supplies ready-to-use single board computer, flight software such as boot loaders and drivers, and advanced software development tools such as debuggers and simulators. Their processor solutions combine high performance with low power consumption, and their IP cores support portability between technologies.
“Cobham has a longstanding tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry. For nearly 20 years, Cobham’s LEON processors, which are based on the SPARC ISA, have been used in RadHard and High Reliability microelectronics solutions in hundreds of spacecraft and terrestrial applications due to their rich feature set and dependability,” said Kevin Jackson, vice president and general manager, space and semiconductor solutions, Cobham Advanced Electronic Solutions. “Our new LEON5 achieves a major improvement in terms of compute performance, while simultaneously allowing a smooth upgrade path and software re-use for our existing LEON user base.”
“Xilinx’s collaboration with Cobham Gaisler allows us to bring some of the latest scalar processor technologies to our space-grade FPGA product families,” said Minal Sawant, System Architect, Space Products, Xilinx. “Their new LEON5 processor IP core complements Xilinx’s existing portfolio to provide the broadest IP solution to our space customers. Prior LEON series processors continue to be supported on many previous generation Xilinx FPGAs, while the new LEON5 state of art spaceflight processors, when implemented on our forthcoming new space parts, will provide unprecedented flexibility to meet varying on-board processing needs on next generation high performance sophisticated payloads systems.”
“Cobham is delighted to add our first in-house implementation of a RISC-V processor core to our existing processor portfolio,” said Sandi Habinc, General Manager, Cobham Gaisler solutions. “The addition of a product line of RISC-V processors strengthens Cobham’s abilities to offer reliable processor solutions to customers also outside the space domain.
“Xilinx is pleased to see Cobham Gaisler expand its offering with NOEL-V to bring the RISC-V ISA to its processor IP portfolio,” said Simon George, Director Embedded Platforms Marketing, Xilinx. “As an emerging open source processor architecture, NOEL-V is now a viable option for soft core processing in our space focused FPGA portfolio.”
Both processors will be fully integrated with Cobham’s GRLIB VHDL IP core library. GRLIB offers a plenitude of interfaces and functions such as high-speed serial interconnect, encryption, compression, etc., to which the RISC-V processor can interface
For more information about Cobham’s processor products, please visit www.cobham.com/Gaisler.