The rollout of the first mmWave 5G systems has begun. While many of the initial installations provide fixed broadband access, mmWave 5G also provides broadband access to mobile terminals. To address the difficulties of non-line-of-sight communications at mmWave, 5G mobile terminals will adopt a phased array or switched antenna topology. This will require multiple, identical RF front-end components, such as power amplifiers (PA). As well as having adequate gain, output power and linearity, the PA demanded by 5G terminals must be efficient, compact and low-cost. The availability of multi-channel mmWave components is key to achieving these goals.
This article describes the design and evaluation of a four-channel, SMT-packaged PA for the 28 GHz 5G NR band (i.e., 27.5 to 28.35 GHz), offering a compelling solution for 5G terminals. The PA was fabricated on Sanan IC’s P15EP process, a 4 V, 0.15 µm enhancement-mode GaAs PHEMT process. The four-channel PA is integrated on a single die and assembled in a 5 mm x 5 mm, plastic overmolded, SMT-compatible QFN package, making it compact and low-cost. It offers good performance from 26 to 29 GHz, covering the full 28 GHz 5G band.
Figure 1 4-channel PA block diagram.
PA ARCHITECTURE
Figure 1 shows the block diagram of the four-channel PA IC. It comprises two halves that are the mirror image of each other, and each half contains two identical channels: the top contains channels 1 and 2, the bottom channels 3 and 4. Each channel consists of a three-stage PA with an integrated output power detector. The RF inputs and outputs of each channel are on the left- and right-hand sides of the die, respectively. Channels 1 and 2 share the same DC bias pads, which are shown on the top side of the block diagram. One pad provides the gate bias for stages 1 and 2 of channels 1 and 2, another the gate bias for stage 3 of channels 1 and 2. Similarly, one pad provides the drain voltage for stages 1 and 2 of both channels, and a separate pad provides the drain voltage for stage 3 of both channels. Sharing the DC bias pads enables a more compact form factor. The nominal drain supply voltage is +4 V, and the gate bias voltages are adjusted to achieve the target quiescent currents: 160 mA total for stages 1 and 2 of both channels and 240 mA total for stage 3 of both channels. At these supply currents, each transistor is biased at a nominal current density of 100 mA/mm.
The DC outputs of the RF power detectors for channels 1 and 2 are located on the top side of the die. Separate uncompensated detector outputs are provided for channels 1 and 2, with a detector reference voltage shared by the two channels. A temperature compensated detector output is created by taking the difference between the detector reference voltage and the uncompensated detector output for each channel.
Figure 2 4-channel PA die.
Figure 3 SMT-packaged PA on an evaluation board.
With the mirror symmetry of the IC, the DC bias and power detector circuit and layout for channels 3 and 4 are the same as for channels 1 and 2, with the DC pads located on the bottom side of the block diagram (see Figure 1). As the PA was designed with an enhancement-mode process, no negative voltages are required. Commercial multi-channel digital-to-analog converters (DAC) are used to bias the PA gates, with analog-to-digital converters (ADC) used to monitor the power detector outputs.
Figure 4 Measured S-parameters.
Figure 5 Measured vs. simulated gain at 100 mA/mm bias.
