CTS Corp. announced a new family of phase-lock-loop (PLL) modules, with two initial members, models VFJA1490 and VFJA1491, both supplied in miniature surface-mount packages measuring just 9 x 14 mm. The VFJA1490 models work with LVPECL, LVCMOS, and sinewave inputs from 10 to 200 MHz and provide LVPECL outputs at frequencies to 1 GHz with extremely low jitter of 65 fs measured 12 kHz to 20 MHz from the carrier. The phase noise is also low, at just -145 dBc/Hz offset 100 kHz from a 500-MHz carrier. The VFJA1491 models operate with LVPECL, LVCMOS, and sinewave inputs from 10 to 200 MHz and deliver LVPECL or LVCMOS outputs at frequencies to 200 MHz. The jitter is also low, just 90 fs offset 12 kHz to 20 MHz from the carrier, while phase noise is only -155 dBc/Hz offset 100 kHz from a 156.25-MHz carrier.
With increased demand for high-speed data and video transmissions, communication infrastructure (wireless and wireline) equipment manufacturers must design systems for higher transmission bit rates. In other words, operating at higher frequencies with lower noise levels. Systems operating at high transmission bit rates are sensitive to accumulated noise (internal to systems or external from input sources)-jitter tolerance and jitter generation. Such systems require low-noise internal clocks and low-noise PLL circuits. While system clocks are designed to operate at low frequencies, data modulation is set to operate at high frequencies so that more data and video could be packed at each cycle. Current architectures utilize IEEE 1588 backhaul timing standards to lock individual nodes to the main system clock while each node modulates the data while using PLL and multiplication techniques.
Current PLL-based solutions include self-contained devices (VCXO and a PLL ASIC integrated) as well as PLLs which require separate VCXO and loop filters to be added. In most cases, integrated solutions lack the performance to comply with low-noise requirement at the high frequencies. To meet modern telecommunications systems requirements, CTS Corporation’s VFJA1490 and VFJA1491 series PLL modules employ a unique design approach to attenuate system/reference noise as well as translate/multiply low-frequency reference input signals to higher stabilized output frequencies.
CTS’s new miniature PLL module family features two prime members, models VFJA1490 and VFJA1491:
1. VFJA1490 series --9x14 mm:
- a. Output frequencies to 1 GHz
- b. LVPECL outputs
- c. Phase noise at 100 kHz offset reaching -145 dBc/Hz (at 500 MHz carrier)
- d. Jitter of 65 fs from 12 kHz to ~20 MHz
- e. Input frequencies of 10 MHz to ~200 MHz (LVCMOS, LVPECL, sinewave)
2. VFJA1491 series – 9 x 14 mm:
- a. Output frequencies to 200 MHz
- b. LVPECL, LVCMOS outputs
- c. Phase noise at 100 kHz offset reaching -155 dBc/Hz (at 156.25 MHz carrier)
- d. Jitter of 90 fs from 12 kHz to ~20 MHz
- e. Input frequencies from 10 MHz to ~200 MHz (LVCMOS, LVPECL, sinewave)
- Small Cells
- Wireless Communication
- Broadband Access
- Microwave PTP & PTMP
- Military Communication
- Base Stations
- Digital Video
- Test and Measurement
- Radar systems
For more details visit http://www.ctscorp.com/connect_product_line/timing-modules/.