The ever-increasing demand for data on the world’s cellular networks has operators searching for ways to increase capacity 5000× by 2030.1 Getting there will require a 5× increase in channel performance, a 20× increase in allocated spectrum and a 50× increase in the number of cell sites. Many of these new cells will be placed indoors, where the majority of traffic originates, and fiber is the top choice to funnel the traffic back into the network. Yet there are many outdoor locations where fiber is not available or is too expensive to connect; for these situations, wireless backhaul is the most viable alternative.

Figure 1

Figure 1 Functional block diagram of the two-way 60 GHz link.

Unlicensed spectrum at 5 GHz is available and does not require a line-of-sight (LOS) path. However, bandwidth is limited and interference from other users of this spectrum is almost guaranteed, due to heavy traffic and wide antenna patterns. 60 GHz is emerging as a leading contender to provide these backhaul links for the thousands of outdoor cells that will be required to meet capacity demands. This spectrum is also unlicensed. Unlike frequencies below 6 GHz, it contains up to 9 GHz of available bandwidth. Moreover, the high frequency allows for very narrow and focused antenna patterns that are somewhat immune to interference; however, they do require LOS paths.

Modems based on FPGAs and systems on a chip (SoC) are increasingly used in wireless backhaul solutions, since platforms using them can be modular and customizable, reducing the total cost of ownership for OEMs. For the radio portion of these links, transceivers have been integrated into silicon ICs and assembled in low cost, surface-mount packages. Commercial parts are now available to build a complete two-way data link at 60 GHz, filling each of the functional blocks in Figure 1. Developed by Xilinx and Hittite Microwave (now Analog Devices), the design includes a Xilinx modem and Analog Devices millimeter wave radio. This link meets the performance and flexibility requirements of the small cell backhaul market.

As shown in Figure 1, two nodes are required to create the link. Each node contains a transmitter with a modulator and its associated analog chain and a receiver with a demodulator and its associated analog chain. The modem card is integrated with analog and discrete devices.  It contains oscillators to ensure the accuracy of frequency synthesis, and all the digital functions are executed in an FPGA or SoC. This single-carrier modem core supports modulations from QPSK to 256 QAM in channel bandwidths up to 500 MHz, achieving data rates as high as 3.5 Gbps. The modem supports both frequency-division duplex (FDD) and time-division duplex (TDD) transmission. Robust modem design techniques reduce the phase noise implications of the local oscillators. Powerful low-density parity check (LDPC) coding is included for improved performance and link budget.

Figure 2

Figure 2 The wireless digital modem is implemented with a programmable SoC.


The millimeter wave modem enables infrastructure suppliers to develop flexible, cost-optimized and customizable links for their wireless backhaul networks. The modem is fully adaptive, low power and small, and can be used to deploy indoor and full outdoor point-to-point links, as well as point-to-multipoint links. The solution allows operators to build scalable and field-upgradable systems.

Figure 2 shows a functional block diagram of the digital modem, which is implemented as an SoC. Besides the programmable logic (PL), the platform’s scalable processing system (PS) contains dual ARM Cortex-A9 cores with integrated memory controllers and multistandard I/Os for peripherals. The SoC platform is used to perform various data and control functions and to enable hardware acceleration. An integrated millimeter wave modem complete with PHY, controller, system interfaces and packet processor is included.

Based on the required architecture, different modules can be inserted, updated or removed. For example, an XPIC combiner could be implemented to enable the modem to be used in a cross-polarization mode with another modem. The solution is implemented in the PL, where serializer/deserializer (SerDes) and I/Os are used for various data path interfaces, such as between the modem and packet processor, the packet processor and memory, inter-modem or DAC/ADC.

Other important features of the modem IP include:

  • Automatic hitless and errorless state switching through adaptive coding and modulation (ACM) to keep the link operational
  • Adaptive digital closed-loop predistortion (DPD), to improve RF power amplifier efficiency and linearity
  • Synchronous Ethernet (SyncE), to maintain clock synchronization and
  • Reed Solomon or LDPC forward error correction (FEC), based on the design requirements.

LDPC FEC is the default choice for wireless backhaul applications, while Reed Solomon is preferred for low-latency applications such as front-haul. LDPC implementation is highly optimized and exploits FPGA parallelism for computations done by the encoders and decoders. The result is noticeable SNR gains. Different levels of parallelism are applied by varying the number of iterations of the LDPC core, which optimizes the size and power of the decoder. The design can also be modeled based on channel bandwidth and throughput constraints.

Figure 3

Figure 3 Functional block diagram of the 60 GHz transmitter IC.

This modem solution comes with a graphical user interface (GUI) for both display and debug. It is capable of high level functions such as channel bandwidth and modulation selection as well as low level ones such as setting hardware registers. To achieve 3.5 Gbps throughput, the modem IP runs at a 440 MHz clock rate. It uses five gigabit transceivers (GT) for connectivity interfaces to support the ADCs and DACs and a few more GTs for 10 GbE payloads and CPRI interfaces.


A second-generation SiGe chipset was optimized for 60 GHz small cell backhaul applications. The transmitter chip is a complete analog baseband to millimeter wave up-converter. An improved frequency synthesizer covers 57 to 66 GHz in 250 MHz steps, with low phase noise that can support modulations up to at least 64 QAM. The output power was increased to roughly 16 dBm linear, and an integrated power detector monitors the output power to maintain the output within regulatory limits. The transmitter chip offers either analog or digital control of the IF and RF gains. Analog gain control is sometimes needed when using higher-order modulation, since discrete gain changes can be mistaken for amplitude modulation, leading to bit errors. A built-in serial peripheral interface (SPI) supports digital gain control.

Figure 4

Figure 4 Functional block diagram of the 60 GHz receiver IC.

For applications requiring even higher-order modulation in narrow channels, an external PLL/VCO with lower phase noise can be injected into the transmitter, bypassing the internal synthesizer. Figure 3 shows a block diagram of the transmitter chip, which supports up to 1.8 GHz of bandwidth. An MSK modulator option enables low cost data transmissions up to 1.8 Gbps without the need for expensive and power-hungry DACs.

A receiver chip complements the transmitter IC (see Figure 4) and is, likewise, optimized to meet the demanding requirements of small cell backhaul applications. The receiver features a significant increase in the input P1dB to -20 dBm and IIP3 to -9 dBm to handle short-range links, where the high gain of the dish antennas leads to high signal levels at the receiver input. Other key features include a low 6 dB noise figure at maximum gain, adjustable lowpass and highpass baseband filters, either analog or digital control of the IF and RF gains and the same new synthesizer design found in the transmitter chip, to support 64 QAM modulation over 57 to 66 GHz. The receiver also contains an AM detector to demodulate amplitude modulation such as on/off keying (OOK) and an FM discriminator to demodulate simple FM or MSK modulation. This is in addition to the I/Q demodulator that is used to recover the quadrature baseband outputs for QPSK and more complex QAM modulation.

Both transmitter and receiver ICs come in a 4 × 6 mm wafer-level BGA package. Surface-mount packaging supports low cost manufacturing of radio boards for backhaul applications.

Figure 5

Figure 5 A reference design for the 60 GHz link based on Xilinx and Analog Devices ICs.

Figure 5 shows a block diagram of an the millimeter wave modem and radio system. In addition to the FPGA, modem software and millimeter wave chipset, the design contains a dual-channel, 12-bit 1 GSPS ADC; a quad-channel, 16-bit, up to 2.8 GSPS Tx DAC; and an ultra-low jitter clock synthesizer, with support for the JESD204B serial data interface employed on both the ADC and DAC ICs. A demonstration platform (see Figure 6) was jointly created by Xilinx and Analog Devices. It includes the FPGA-based modem on a Xilinx development board, a standard FMC board containing ADCs, DACs and clock and two radio module evaluation boards. The platform includes a laptop for modem control and visual display and a variable RF attenuator to replicate the path loss of a typical millimeter wave link. The FPGA on the development board executes the WBM256 modem firmware IP. A standard FMC mezzanine connector on the development board connects to the baseband and millimeter wave radio boards. The millimeter wave modules snap onto the baseband board. The modules have MMPX connectors for the 60 GHz interfaces and SMA connectors for optional use of an external local oscillator. This platform contains all the hardware and software needed to demonstrate point-to-point backhaul connections of up to 1.1 Gbps in 250 MHz channels for each direction of an FDD link.

Figure 6

Figure 6 60 GHz link demonstration platform.


The experience developing the modem, transceivers and demonstration platform yielded the following considerations for designers:

Since they’re highly modular and customizable, FPGAs can reduce the cost to build platforms for wireless backhaul. When choosing commercial parts for a millimeter wave modem solution for small cell, select power-efficient FPGAs/SoCs and high performing wideband IP cores. High speed is also a factor to consider when selecting GTs for wideband communications and switching functions. Look for a solution that can scale to support multiple product variations on the same hardware platform, from lower end, small cell backhaul radios that operate at a few hundred megabits per second to high performance systems carrying 3.5 Gbps.

For the radio, transceiver ICs in surface mount packages will lower the cost of manufacturing. Parts currently on the market will meet the power, size, flexibility and functionality requirements for small cell wireless backhaul. The high-performing data converters and clock-management ICs that are required to complete a wireless backhaul link are also commercially available.


  1. “Evolutionary and Disruptive Visions Towards Ultra High Capacity Networks,” IWPC, April 2014.