The design of a low power high gain current-reused CMOS low noise amplifier (LNA) for GPS applications employs a novel current-reused (CR) topology with three cascaded common source (CS) gain stages without increasing power dissipation. The LNA is fabricated using a 0.20 µm RF SOI CMOS process. It consumes 4.5 mA quiescent current from a 1.5 V supply. It has 26.4 dB of power gain, a 1.31 dB noise figure, -25.5 dBm P1dB and -12.8 dBm IIP3 at 1.575 GHz. Input/output return loss is 15.9 dB/13.2 dB respectively.
With advances in wireless communication systems technology in recent years, many wireless electronic products such as smart phones have become more portable, power-saving, and capable of providing a greater variety of services. Low noise figure (NF), low power consumption, high gain and high linearity, i.e., third-order intercept (IP3), for RF amplifiers such as LNAs are critical requirements that are nearly impossible to satisfy simultaneously. To date, a two-pronged design strategy has been used to achieve these goals: one is to optimize for high gain and low noise but with low linearity for small signals with low interference; the other is to optimize for low gain with high linearity but with high noise for large signals with high interference.
GPS has become an indispensable function for tracking and navigation in mobile communications applications.1 The GPS market demands lower power and lower cost solutions for integrated receivers while the trend towards ultra-miniaturization requires the use of fewer, if any, external components.2 To detect weak satellite signals, a GPS receiver must have superior sensitivity.3 It is well known that the sensitivity of a receiver is determined mainly by the first amplifier, i.e., the LNA.4 This first amplifier stage should have a very low NF and high gain, thereby preventing the following stages from significantly degrading the signal-to-noise ratio.5,6,7 For that reason, previous GPS radios have been implemented in a bipolar or BiCMOS process due to its low noise characteristics.3,5 Furthermore, the GPS RF front-end module must occupy the smallest possible area for integration in a multimode environment.1 RF silicon on insulator (RF SOI) CMOS technology is now becoming an attractive RF front-end process for its low loss, low noise and high linearity.
This article describes an energy-efficient GPS receiver that employs a current reuse architecture; i.e., multiple RF circuits that use the same DC bias currents stacked to form a single cell.2,5,7 Among the variety of conventional LNA input topologies, such as resistive match common source (CS), common gate (CG), and resistive feedback CS topologies, the source inductive degeneration CS input topology shows the most promise for this application. At the circuit level, the current-reused structure is adopted to provide low power consumption and high gain simultaneously. The design and implementation of a novel 1.575 GHz CR topology having three cascaded gain stages without increasing power dissipation not only demonstrates the feasibility of the design methodology but also achieves high gain performance simultaneously with low power consumption.
The evolution of LNA topology is from conventional cascade to CMOS inverter and CR. Conventional LNA topologies, such as cascade, cascode, and resistive feedback, have been proposed to achieve superior performance. Among the variety of topologies, CR shows the most promise for achieving high gain and low power simultaneously. Figure 1 shows a typical CR LNA topology composed of two CS stages in which the bias current of transistor Min is shared by transistor M3 resulting in double the gain with the same bias current to the cascade.
Under similar bias conditions, amplifier gain can be further enhanced by increasing the number of cascaded stages. In this work, an enhanced CR topology with three cascaded CS gain stages is presented. A complete circuit schematic of the LNA, equivalent to a three stage CS amplifier, is shown in Figure 2. The bias voltage and current of the second stage (M2) and third stage (Mo) are the same and they together share bias current with the input stage (Min). The transconductance of M3 in Figure 1, gm3, is equally shared by M2 and Mo in Figure 2, i.e., gm2 = gmo = 0.5 gm3. This novel design realizes a three CS amplifier cascade with the same current consumption of a typical CR LNA. Figure 3 shows a circuit schematic of the equivalent three-stage cascaded amplifier with input, output, and inter-stage matching networks that provides high gain with low power consumption for GPS applications.
A CS topology is used for the first stage (Min) to achieve simultaneously low noise figure and good input matching performance. The input matching network for Min comprises an input series gate inductor L1, source-degeneration inductor L2, the Cgs of Min and an added capacitor Cex. This makes an LC ladder filter resonating at 1.575 GHz to achieve an input return loss greater than 10 dB. As the first stage of the proposed LNA, a power constrained simultaneous noise and input matching (PCSNIM) technique is used to achieve good input return loss (S11) with low power consumption. The transistor size and Q of the input matching network can be decoupled with the extra capacitance for noise optimization and input matching at low power. L3 and L4 act as RF chokes to provide DC current as well as interstage matching. C3 is an AC-grounded capacitor whose capacitance is chosen as large as possible. L5, C5 and C6 are designed for matching of the output CS stage (Mo). C2 and C4 are for interstage signal coupling and interstage matching.
In order to provide a comparison of gain and power consumption, the typical CR LNA in Figure 1 is designed and built. An approximate small-signal model is also developed for the analysis and comparison of power gain. For a common source LNA, the voltage gain is AV = gmeff · Rload and the gains of a typical CR (ATCR) and this design (ANCR) are derived in Equations 1 and 2. This shows that the gain of the new LNA is higher than the typical CR LNA due to CR gain enhancement. Noting that gm3=2gm2=2gmo, the boosted gain (AE) is derived in Equation 3. In this new design, the transconductance gm3 ≈ 3di and Rload = C5||L5 <200 Ω, so it improves the gain by 8 dB.
The new CR LNA and the typical CR LNA are fabricated using the HHGrace 0.20 µm 1P3M RFSOI CMOS process for a 1.575 GHz band GPS application. The aspect ratios of the transistors Min, M2, Mo and M3 are 320 µm/0.20 µm, 200 µm/0.20 µm, 200 µm/0.20 µm and 400 µm/0.20 µm, respectively. C3 is a 4 pF capacitor in the second and third (AC grounded) CS stages. R1, R2 and R3 are 50 kΩ resistors providing bias voltage and RF signal blocking, eliminating the need for an RF choke. All capacitors are metal-insulator-metal and all inductors are implemented on the top metal (thickness of 4 µm) layer in octagonal formsto minimize resistive losses. The substrate is a trap-rich silicon on insulator (TR-SOI) wafer with good performance for noise and harmonic linearity.
Both the new CR GPS LNA and typical CR LNA consume 4.5 mA from a 1.5 V supply. Simulated and measured S-parameters and NF for the new CR GPS LNA are shown in Figure 4, while Figure 5 shows simulated and measured input P1dB and IIP3. Both figures show good agreement between measurement and simulation. Measured small signal power gain (|S21|) and NF are 26.4 dB and 1.31 dB, respectively, at 1.575 GHz. Measured input return loss (|S11|) is about 15.9 dB and output return loss (|S22|) is about 13.2 dB. The measured input P1dB and IIP3 are -25.5 dBm and -12.8 dBm respectively. Table 1 summarizes the characteristics and performance of previously reported GPS LNAs compared with the typical CR LNA and the new CR LNA described in this work. Figures of merit (FOM) are used for benchmarking LNA designs, and are defined as:
The high gain architecture demonstrates the highest gain performance with the best FOMs.
A GPS LNA achieves high gain simultaneously with low power consumption as compared to previously reported CMOS LNAs for GPS applications. Gain enhancement is realized with the three CS cascade amplifiers and power consumption is economized with the CR topology. The design and implementation of a 1.575 GHz CR desgn with three cascaded gain stages is described. The LNA not only demonstrates the feasibility of the design methodology but also achieves a 1.31 dB NF, -12.8 dBm IIP3, and 26.4 dB power gain. It consumes 4.5 mA from a 1.5 V power supply.
The authors would like to thank Heng Zhang, Guojun Liu and Jun He for their valuable contributions. This work was supported by HHGrace and SIMIT.
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Ruofan Dai received his B.S. degree in microelectronics at Sichuan University, Chengdu of China in 2011. He is currently working toward his Ph.D. degree at Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai, China. His current research interest is in Si/SOI CMOS analog/RF integrated circuit design, especially for high speed SAR ADC and RF front-end applications.
Yunlong Zheng received his B.S. degree in electronic engineering from Chongqing University of Posts and Telecommunications, Chongqing, in 2010. He is currently working towards his Ph.D. degree in Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai. His current research interest is in analog and radio frequency integrated circuit design.
Shichang Zou, academician of the Chinese Academy of Sciences graduated from Tangshan Jiaotong University in 1952 and received his associate doctor’s degree at Moscow Nonferrous Metals College in 1958. He currently serves as researcher and Ph.D. supervisor at Shanghai Institute of Micro-System and Information Technology, CAS of China. His research interests include SOI material and Si/SOI CMOS analog/RF circuit design.
Weiran Kong received his B.S. degree in Physics from Nankai University of China in 1985 and received his Ph.D. degree in applied physics at Oregon Graduate Institute of Science and Technology in 1995. He also worked forSun Microsystems, LSI Logic and ISSI. He joined Shanghai Huahong Grace Semiconductor Manufacturing Corp. in 2003, where he is currently vice president of technology and development. His research interests include design of flash memory, logic and mixed signal integrated circuits.