Agilent Technologies announced that TSMC has certified the accuracy, performance and compatibility of Agilent’s GoldenGate RFIC circuit simulator for baseband designs targeting TSMC’s 65LP nanometer (nm) and 40LP nm processes. The TSMC SPICE Tool Qualification Program targets TSMC’s 65/40 nm and smaller geometry process technologies, delivering improved device model accuracy, enhanced simulation efficiency and compatibility, and enabling faster time-to-market and first-pass silicon success.
“As part of the TSMC Open Innovation Platform, I am pleased to announce that Agilent’s GoldenGate RF/mixed-signal simulator has met the stringent 65/40LP nm baseband SPICE Tool Qualification Program requirements for accuracy and compatibility,” said Tom Quan, Deputy Director of Design Service Marketing at TSMC. “GoldenGate qualification reports for TSMC’s 65/40nm processes have been posted on TSMC-Online.”
“With the ever-increasing complexity and operating characteristics for next-generation wireless ICs, foundry and EDA collaboration is essential for successful RFIC designs in these leading-edge technology nodes,” said Paul Colestock, RFIC Product Marketing Manager with Agilent’s EEsof EDA division. “We are pleased with the certification of GoldenGate for these advanced RFIC nodes as well as the relationship we have established with TSMC on several fronts that will benefit our mutual RFIC customers.”
GoldenGate is an advanced simulation and analysis solution for integrated mixed-signal RFIC design. Its unique simulation algorithms are optimized for the challenging demands of today’s complex RFICs, and its capacity enables full characterization of complete transceivers, including parasitics, prior to tape-out. GoldenGate takes advantage of frequency-domain, time domain and mixed-signal simulation technologies to ensure proper device operation, increased manufacturability and reduced design spins.
GoldenGate also includes a suite of automation tools to increase overall simulation coverage developed with the RFIC designer in mind. This suite helps designers launch multiple, parallel simulations, quickly analyze circuit performances and diagnose problems with mixed-signal RFICs earlier in the design cycle.