Coplanar waveguides are widely used in MMICs as interconnects and matching networks. Designing low loss, multifunctional and highly integrable transmission lines is a key factor in obtaining high performance from MMICs in silicon technology.1 Nevertheless, the low resistivity of a standard silicon substrate deteriorates the performance of on-chip passive components.2,3 To overcome the problem of high dielectric loss of the low resistivity silicon (LRS) substrate, a thick SiO2 layer4 and a spin-coated thick polyimide layer5 are utilized in microwave applications. A high resistivity silicon substrate is also used in the microwave region because of its low dielectric loss.6,7

In order to investigate the substrate effect on the transmission performance of the CPW line systematically, low resistivity Si (LRS) substrate, SOI substrate and HR SOI are employed in the experiments. The CPW structures fabricated on these substrates are shown in Figure 1. The samples A1 and A2 are built directly on LRS substrates, A3 is fabricated on SiO2, A4 on polyimide with a metal shield layer, and B1 and B2 are made on LR SOI or HR SOI substrates. The insertion losses of the CPW lines are greatly decreased when a shield metal layer and polyimide interlayer are on the LRS substrate. A novel HR SOI structure, with a buried oxide layer in silicon and a HR substrate, shows a low attenuation of the CPW lines.

Fig. 1 CPW structures.

Experiment

All the CPW lines were designed with a 50 ? characteristic impedance. The metal is aluminum with a thickness of 0.6 ?m. The width of the centerline is 0.1 mm and the gaps are 0.08 mm wide. The length of all the lines tested was 3 mm. Two categories of substrates were used: bulk LRS substrates with resistivities of 0.5 ? cm and 20 ? cm, and separation by implanted oxygen (SIMOX) SOI substrates with resistivities of 20 W cm and 1000 ? cm. The buried oxide (BOX) thickness is 380 nm and the top silicon thickness is 200 nm. The samples, with different substrates and structures, are summarized in Table 1. The impact of the ground line width on the CPW transmission behavior was also investigated in this experiment. The ground line width was varied from 200 to 600 ?m.

The CPW transmission characteristics were measured with an Agilent HP8722D vector network analyzer and probe station. The probe was calibrated before the measurements.

Results and Discussion

CPW on Bulk Silicon Substrates

The measured results taken on the structures A1 and A2 are shown in Figure 2. The attenuations of A1 and A2 are 2.9 dB/mm and 1.7 dB/mm at 2 GHz, respectively. The insertion loss of CPW on low resistivity silicon is high, which may be caused mainly by the substrate loss. There is a high concentration of free electron carriers in bulk silicon substrates. The electromagnetic coupling produces an induced current in the bulk silicon substrate, which induces an alternate polarization of the dielectric molecules and collision of crystal lattices, resulting in high losses. In addition, when the resistivity of the substrate increases to 20 ? cm, the attenuation of the CPW line decreases to 1.7 dB/mm. Increasing the resistivity can reduce the substrate loss.

Fig. 2 Measured losses of the CPW lines on A structures.

In order to isolate the passive components from the lossy substrate, a layer of silicon dioxide, approximately 1 mm in thickness, is deposited on the LRS substrate (sample A3). The curve A3 shows that the attenuation is 0.7 dB/mm at 2 GHz, 65 percent lower than that of A2. The insulating layer of silicon dioxide can prevent the propagation of the electromagnetic waves in the substrate, which results in a lower insertion loss.

To improve the behavior of CPW on low resistivity silicon, a 0.6 mm thick ground plane, made of aluminum, is introduced in the LRS, on which a 10 mm thick polyimide layer is deposited (sample A4). The curve A4 shows that the attenuation is 0.06 dB/mm at 2 GHz. The ground plane completely shields the electromagnetic fields from the lossy bulk silicon substrate. The attenuation is greatly reduced compared to sample A2.

CPW on SOI

The CPW transmission performance on SOI substrate was also investigated in the experiment. They were fabricated directly on SOI substrates with resistivities of 20 ? cm and 1000 ? cm (samples B1 and B2). The measured results are shown in Figure 3. At 2 GHz, the attenuation for B1 is 1.1 dB/mm and 0.13 dB/mm for B2. The attenuation of the CPW line made on SOI is 45 percent lower than that of the bulk silicon of the same resistivity, 20 ? cm. The buried oxide layer in SOI offers a complete isolation between the top silicon and the bulk substrate and eliminates the substrate current injection path.

Fig. 3 Measured losses of the CPW lines on B structures.

A high resistivity substrate can be selected for SOI to further reduce the CPW loss at high frequency, which is impossible for bulk technology due to latch up concerns. When the SOI substrate resistivity increases to 1000 ? cm, the attenuation decreases to 0.13 dB/mm, as shown in curve B2, reduced by 88.2 percent, which is comparable to the structure with a shield layer (0.07 dB/mm). With HR SOI, the substrate loss can be reduced and the performance of the passive component is improved greatly. The results of A4 are also shown for convenient comparison. The attenuation of B2 is a little higher than that of A4 between 2 and 5 GHz, but when the frequency increases, the attenuation of B3 is lower than A4, which means that high resistivity SOI has the advantage in higher frequency range applications.

The transmission line attenuation is attributed to the conduction and dielectric losses.8 The CPW lines used here are 0.6 ?m thick, which is only about one skin depth, that is to say, only 1/e of the current can pass through the CPW lines, which will increase their loss. If the CPW lines are made thicker, the attenuation can be further reduced. In addition, if some isolation is added between the SOI substrate and the CPW line, the behavior of the CPW can be improved. Still, the HR SOI has great potential in improving the performance of passive components at high frequencies.

The Impact of the Ground Line Width on CPW Lines

Figures 4a and b show the attenuation of the CPW lines with ground line widths of 200, 300 and 600 ?m on Si and SOI substrates, respectively. The Si substrates are 20 ? cm and the SOI are 1 k? cm. The attenuation of the CPW line is the lowest when the ground line is 300 ?m wide and largest when the ground line is 600 ?m. The electromagnetic energy radiation declines when the ground line width increases. When the ground line width increases to a certain extent, however, a higher mode appears, which will increase the loss of the CPW lines again.

Fig. 4 Insertion loss of CPW lines with different ground line widths; (a) on LRS substrate and (b) on HR SOI substrate.

Conclusion

The transmission loss properties of CPW on bulk silicon and LR and HR SOI substrates were investigated systematically in this article. By isolating the CPW line and the bulk Si substrate with SiO2 or a metal shield and polyimide layer, the performance of the CPW line is greatly improved. An SOI substrate with a buried oxide layer in silicon can eliminate the current path and improve the performance of passive components. With the choice of a high resistivity substrate, the insertion loss of CPW lines on HR SOI was reduced and demonstrated the prospect of attracting applications in the gigahertz field.

Acknowledgment

This work was supported by the National Natural Science Foundation of China (No. 10474076).

References

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