ADCIt is a known fact that time interleaving of Analog-to-Digital Converters (ADC) is used to increase sampling rate of modern high-performance digitizers. A recent high performance example is the 10-bit digitizers from Guzik Technical Enterprises (GTE) that feature Keysight Technologies ADC Integrated Circuit (IC) where 160 individual ADC are interleaved to achieve sampling at up to 64 Gsa/s (160 “slices” sampling at 400 Msa/s) forming two analog channels at 32 Gsa/s each. Time interleaving that large number of ADCs makes it challenging to achieve high Spurious-Free Dynamic Range (SFDR). Patented digital equalization technology[i] is used to reduce mismatch between slices, non-flatness of Frequency Response (FR) and Group Delay (GD)[ii] of the Digitizer, to create a calibrated baseband receiver in DC to 10 GHz band with input signal range from Fig-32 to +22 dBm. The same technology can be extended to equalize FR and GD of up and down-converters which are working together with the digitizer to create desired “reference calibration plane” at the down-converter input (RF reference plane) or at the Up-converter input (IF reference plane).


28 GHz frequency band down-converter FR and GD measurement setup

The simplified block diagram of measurements is shown on Figure 1.

Fig 1
Fig. 1

FR measurement is a relatively simple procedure: signal from CW generator is applied through the waveguide Band Pass Filter (BPF) to down-converter RF input. The measurements are performed in BPF bandwidth of 27.4 to 28.35 GHz. The frequency steps of CW generator were chosen small enough to measure details of the frequency response. About 1200 measurements with frequency step 1 MHz was conducted. Note that an analog sine wave signal generator with NIST traceable calibration was used to measure the frequency response.

The Digitizer has been calibrated and FR and GD have been equalized prior to these experiments. To measure GD, a GTE proprietary signal source was used. The measured FR and GD are shown on Figure 2 and 3, respectively. On the same figures the equalized FR and GD are shown for 1279 tap equalizer. The typical non-flatness of FR and GD are ±0.1 dB and ±100 ps, respectively.

Fig 2
Fig. 2

Fig 3
Fig. 3

Below the FR and GD temperature stability of the Down-converter is plotted. The deviation from equalized FR and GD are shown on Figures 4 and 5, respectively.

Fig 4
Fig. 4

Fig 5
Fig. 5

A Vector Signal Generator (VSG) with low enough base Error Vector magnitude (EVM) in 28 GHz frequency range could not be identified on the market that would make it impossible to measure EVM of the down-converter before and after equalization. For that reason, the calibration plane was moved to the IF input of the up-converter.

28 GHz frequency band UP and Down-converter FR and GD measurements

The simplified block diagram of measurements is shown on Figure 6.

Fig 6
Fig. 6

The CW and GD signals were generated in frequency range 500 MHz to 1.5 GHz such a way that upper sideband at up-converter output was in the BPF passband (see Figure 6). The measurement results of FR and GD are shown on Figure 7 and 8, respectively. On the same figures the equalized FR and GD are shown for 1279 taps equalizer. The typical non-flatness of FR and GD are ±0.1 dB and ±50 ps, respectively.

Fig 7
Fig. 7

Fig 8
Fig. 8

Figures 9 and 10 show how the equalized FR and GD responses are changing with different equalizer number of taps.

Fig 9
Fig. 9

Fig 10
Fig. 10

Figures 11 and 12 show the deviation of equalized FR and GD of up/down converters for different temperatures.

Fig 11
Fig. 11

Fig 12
Fig. 12

The results of the EVM measurements for 16QAM and 64QAM, 625 Msymbol/s modulated signal with Root-Raised-Cosine (RRC) filter roll-off factor of 0.35 for transmit and measurement without and with FR and GD equalization are shown on Figures 13-16 (using Keysight Technologies VSA 89600 Software). Before equalization, EVM is ~11% and after the equalization is ~1% for 16QAM. For 64QAM measured EVM is 8.79% before equalization and ~1% after equalization. The measurements of EVM for different equalizer taps shows that even for 159 taps equalizer EVM is ~1%. Longer equalizer might be needed for wider band up and down-converters.

Fig 13
Fig. 13 EVM 16QAM without equalization

Fig 14
Fig. 14 EVM 16QAM with equalization

Fig 15
Fig. 15 EVM 64QAM without equalization

Fig 16
Fig. 16 EVM 64QAM with equalization

Figure 17 shows how EVM changes over temperature for the up and down-converters from ambient calibration temperature +25 °C.

Fig 17
Fig. 17


The digital equalization technology based on FR and GD measurements of up and down-converters allows for significant reduction in the linear distortions of the test system.

Non-flatness of the FR of the up and down-converters was reduced from ±1.5 dB to ±0.1 dB. Non-flatness of GD was reduced from ±1.25 ns to ±100 ps. As a result, the residual EVM through the up/down-converters in the experiments conducted was reduced from ~11% (-20 dB) to ~1% (-40 dB) for 16QAM, 625 Msymbol/s signal with Root-raised-cosine filter (RRC) factor of 0.35, in the 28 GHz band.

The combination of down-converters and the digitizer with equalizer can be used to create a reference calibration RF reference plane; thus forming a calibrated reference receiver in mmWave bands up to 30 GHz with known FR and GD response. It should be noted that temperature stabilization should be added to the analog up/down-converters to achieve repeatability and high accuracy.

The equalization can be done in the hardware inside the FPGA-based Digital Processor (Guzik ADP7000 Series Digitizer) in real-time for signals with bandwidth up to 2.5 GHz using the patented[iii] Digital Downconverter (DDC). Up-converter (WR28CCU) and down-converter (WR28CCD) were provided by Virginia Diodes, Inc. for experiment and demonstration purposes of the technology.

[i] US Patent 7,408,495 Digital Equalization of multiple interleaved Analog-to-Digital converters

[ii] US Patent 9,933,467 Group Delay Measurement Apparatus and Method

[iii] US Patent 9,634,679 Digital Down Converter with Equalization