Kaben Wireless Silicon Inc., a wireless semiconductor design company, announced that it has successfully produced a VCXO for the timing market in the IBM 7WL process.

The VCXO utilizes Kaben’s patented Delta-Sigma based, Fractional-N synthesis techniques to deliver less than 0.35 ps to a maximum of 0.5 ps of RMS jitter at frequencies up to 1.4 GHz. Systems can suffer from synthesizers with high phase noise and spurs because these translate to jitter in timing systems which lead to unacceptable packet error rates, or low data rate throughput.

“The ultra-low jitter and programmable frequency range makes this VCXO ideal for precision clock conditioning or jitter attenuation applications," said Bill Bereza, Kaben's Director of Marketing. “This product replaces multiple, external VCXOs in multi-band applications. The reduced BoM offers significant cost benefits.”

Through Kaben's patented PLL loop technology, the KWS410 can be integrated as part of a larger SoC thus eliminating the need for off-chip components or may be offered as a standalone IC. This product targets a variety of wireline, optical, wireless and backhaul applications.

Originally designed in the IBM 7WL process, the design can be ported to popular process technologies for any timing application. The silicon-proven VCXO is available as an IP product licensed for integration or to manufacturers as a standalone part.