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Industry News / Amplifiers

LDMOS Technology Solid-State Transmitter for MIDS Communications System

July 12, 2007
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Introduction

From the early 70’s, solid-state pulsed transmitters for primary and secondary radars (IFF-SSR) and also for communications systems (JTIDS) [1], have used silicon bipolar transistors. With such kind of devices, the common working operation mode was class C for optimizing the overall system efficiency and, consequently, reducing the power dissipation [2],. But during the last few years, thanks to the great investments made by the enterprises interested in the mobile phone market, new devices have been developed, the LDMOS transistors. These devices, allow alternative designs to the traditional ones. Most of the manufacturers of solid-state power devices (Philips, MACOM, Integra, APT,...) show datasheets of LDMOS amplifiers working in L-band with better characteristics than bipolar ones, mainly in power gain.

The most important features required for a power device, working with pulsed signals are:

• Output Power

• Power Gain

• Pulse Width

• Duty Cycle

The present article shows the design of a transmitter with an output power of 400 watts for the MIDS Communication System (Multifunctional Information Distribution System), using LDMOS technology. This NATO communication system requires to use of equivalent pulse widths of 3 milliseconds with 20% duty cycles in a frequency band between 950 and 1215 MHz (30% of relative bandwidth), operational features much more restrictive than primary and secondary radars ones. This prototype is a previous work for a complete future amplifier scheme with more than 1Kwatt output power, combining 8 LDMOS amplifiers and only two amplifying stages, allowing and overall power gain of more than 20 dB, which is not possible with bipolar transistors. The purpose of this system is to locate them in military vessels, where a large coverage and a high countermeasures level are required. This kind of transmitters is usually called in the MIDS system High Power Amplifier Group (HPAG).

































Figure 1 shows the main stages of the complete amplifier under development, and also the prototype ones, which is described in this article.

Finally, the overall article scheme pretends to explain in each section the key points of the development of such a transmitter:

• Design of a single amplifier selected for the whole Transmitter

• Analysis sensibility of the polarization point and also the variation of the phase insertion with this point.

• Design of the Binary Power divider-combiner.

• Waveform Modulation in LDMOS amplifier.

(Figure 1 a) Block Scheme of the complete Transmitter b) Prototype Design and Large Signal Characterization of a single amplifier.

The LDMOS device used for the development of this prototype is the Philips BLA0921-250. This amplifier delivers 200 watts of output power, obtaining 12 dB of power gain, working with a pulse width of 3.3 milliseconds and a duty cycle of 22% along the complete MIDS frequency band. There are only few commercial alternatives which fulfill such requirements. MACOM has developed the MR1012D amplifier which is a Class C bipolar transistor with 8dB of power gain but unfortunately only delivers 120 watts at its output port, with these requirements of pulse width and duty cycle. Obviously, is important to select the device capable of deliver the biggest out power because the bigger the output power is, the simpler structure of the transmitter becomes and also the number of devices required reduces.

The amplifier works in Class AB. This mode, suggested by the manufacturer, requires a current consumption even in the absence of input signal. This could be a great problem, but the consumption in the absence of input signal ( Class A) is only 150 mA, which is around 1% of the consumption in large signal operation, 13 A (Class B). As it has been stated, the working duty cycle is approximately 20% then, the mean current consumption for each amplifier will be 2.6 A, becoming the consumption in class A negligible, for power consumption and also for self-heating generation. It has been possible, in laboratory, to work in class B with the BLA0921-250 device, that is, with zero current consumption in the absence of input signal, but as it has been expected, the power gain decreased in 3 dB, losing one of the greatest advantages of the LDMOS amplifiers against the bipolar ones, the power gain.

In order to design the input and output matching networks of the amplifier, the manufacturer gives the large signal impedances, input and output, which have been empirically obtained with the Load-Pull technique. Also a text Fixture is given with a possible design of the impedance matching networks. In this circuitry it can be checked [3] that some resistive elements have been placed for avoiding oscillations in low frequencies. The input and output impedance matching networks should produce, microstrip technology has been chosen, the impedances suggested by the manufacturer but maintaining the resistive elements placed for stabilizing (padding) in low frequencies. Another point to consider is the size of these networks. The dimensions of the microstrip elements should be reasonable for later integration in the overall amplifier. The chosen substrate was Epsilan- 10 with 0.635 mm of thickness, which allows, for the frequency bandwidth chosen, a very good aspect ratio, low losses and has a breakdown field of 45Kv, enough for this application. The synthesis and simulation of these circuits have been made with Advanced Design System (ADS) from Agilent Technologies.

Tables 1 and 2 show the input and output impedances measured by the manufacturer and also the ones implemented with the ADS program. It should be pointed out that the input has been mismatched on purpose for increasing the power gain planarity.









Table 1. Table comparing target impedances and obtained for the input port.









Table 2 : Table comparing target impedances and obtained for the output port.

Figure 2 shows the electric schematic and the photograph of a single amplifier with its impedance networks. This amplifier was tested with a pulsed input signal with 10% of duty cycle and 1ms of pulse width. The measurements are shown in Figure 3 for three different input powers 9, 11 and 13 Watts. The maximum current consumption for the first input was 13 A., so with a drain voltage of 36V giving a drain efficiency greater than 50% for at the frequency band.












Figure 2 – Photograph and electric schematic of the amplifier.





































Figure 3 Output Power and Gain for three different Input Powers.


One key point in the transmitter is to minimize the losses in the combination process. These losses are mainly induced by the insertion phase, gain and polarization point variations between different amplifiers, due to repetitively intrinsic imperfections in the fabrication process. For a better knowledge of these variations, seven transistors have been tested, including some, which had been already used in some previously experiments. The polarization form of BLA0912-250 Philips transistors consist of fixing the drain-source voltage (36 V) and then, select the gate-source voltage till the drain current becomes the desired value to work in Class A, the Idq (drain quiescent current).

In table 3 are summarized the different gate-source voltages needed to obtain 5, 50, 100 and 150 mA in the seven different amplifiers selected.











Table 3 – Gate-Source Voltage variation for the different seven BLA0912-250 devices.


Being the statistical values of the experiment:










Table 4- Statistical Values for Gate to Source Voltages.


The graphical representation of the values can be seen in Figure 4.



















Figure 4 Drain Current versus Gate-Source Voltage for the seven BLA-0912 devices.

Studying the results, and taking as reference 100 mA of Drain current consumption (Class A operation), it can be calculated that the mean value of the Gate to Source voltage needed is 4.15 V and also that the maximum variation of the current for a fixed value of Gate-Source voltage is ±15%, that implies, a maximum variation of ±5% of the current consumption and dissipated power without input signal. This value is negligible against nominal values in large signal operation, 13A. Then, with these values and a duty cycle of 20% and an efficiency of 50%, the mean power dissipation for each amplifier is 46.8 watts.

Then, the variation of the polarization points between different amplifiers is really negligible. By this, a fixed point of polarization can be selected without taking into account the residual Class A current consumption. This simplifies enormously the replacement of a damaged amplifier because is not necessary to characterize it before placing it in the overall structure.

Another key point is the gain variation of the Philips BLA0912-250 amplifiers. In a similar way as before, the small-signal gain variation of the seven devices has been studied. Figure 5 shows the difference between the small signal gain (S21) of each amplifier and the mean gain in the frequency band between 500 and 1500 MHz.























Figure 5 Difference between Small Signal Gain (S21) and the Mean Small Signal Gain for seven BLA0912-250.

As it can be seen in the figure, the difference is not greater than 1 dB implying that the performance of transistors made in different manufacturing processes is very similar.

Finally, the most usual reason of decreasing the gain of a dividing-combining structure is the difference between the phase insertions of different amplifiers. If the phase of the signals at the output of the amplifiers is not equal, the combination process has losses. Figure 6 shows the difference between the phase insertion of each amplifier and the mean phase insertion in small signal measurements. With this results, it can be seen that that the maximum dispersion of the phase insertion for a fixed point of polarization (Vds=36V, Id=150 mA) is less than 10º for the frequency bandwidth, then the maximum losses available in the combination process are negligible, less than 0.13 dB.

























Figure 6 Insertion Phase variation in small-signal operation for seven BLA0912-250 devices.

For all of this, the most important conclusion is that the manufacturing process is repetitive enough for developing a combination structure with solid state amplifiers.

Wideband Binary Divider-Combiner

For the design of a wideband binary divider for the transmitter, we have selected the Gysel structure [4] to divide and combine. This circuit presents the best characteristics because the 50 Ω loads are ground connected, as the Branch-Line circuits do, and also, a large relative bandwidth, as the Wilkinson dividers. The theoretical microstrip structure of a Gysel divider is shown in figure 7 :























Figure7: Gysel Divider

One of the best disadvantages of this divider, is its large size, then developing a transmitter with several amplifiers in a reduced place becomes very difficult. An appropriate redesign of this circuit bending some of the transmission lines was made, in order to reduce the overall surface of the structure and also a best placement of the ports 2 and 3 which are the output ports of the divider, and the inputs of the combiner. Figure 8 shows both designs, on the right, the classical one where the different elements can be easily related to those in figure 7, and on the left the new design minimizing the employed surface.

The experimental behavior of both structures were very similar, with low losses, wide bandwidth and similar frequency response for ports 2 and 3, being the differences very small for modulus and phase. Figure 9 shows the measurements of the “bended Gysel” circuit. The small signal gain for both output ports, 2 and 3, phase difference between ports 2 and 3 and also the input return losses.

































Figure 8:Microstrip Gysel Dividers.(Left :“Bended Gysel”, Right :Typical Gysel).



















Figure 9 : “Bended Gysel” measurements in Microstrip Technology. a) S21 and S31 modulus. b) Phase difference between 2 and 3 ports. c) Input Return Losses.

At first sight, one could assure that this structure has an important problem, the need of two 50 ohms loads. But, each of them should dissipate half the power, in case of any of the amplifiers combined die, graceful degradation. That means that the size and the parasitic effects (undesired capacities reducing the frequency bandwidth) are much less important and do not require added matching networks.

Pulse Width Modulation

One of the great advantages which has the LDMOS against Bipolar technology is the possibility of shaping the pulse width with circuitry that do not consume high levels of current.

Solid-State transmitters with bipolar technology, usually modulates the collector voltage of one of the amplifiers of the transmitter chain in order to control the wave form and the spectrum of the transmitted signal. It is well-known [5] that the Class C amplifiers employed for pulsed transmitters show spectral distortions produced during the fall time of the transmitted pulses. When the input pulse ends, the DC current generated by the rectification of the input signal decreases to zero oscillating into the working frequency bandwidth of the amplifier. This effect is due to internal resonances of the predistortion circuits (bondings and capacitors) of the device. For avoiding these distortions, the amplifier should be excited with a pulse wider than wanted and cut off the collector voltage just a few nanoseconds before the end of the pulse. This technique is known as collector modulation and the circuitry employed should work with the amplifier peak collector current.

In a LDMOS device working in AB class, similar modulations can be made shaping the gate voltage, without the problem of the peak currents manage, because the gate current for LDMOS devices is negligible. Figure 10 shows an example. The input signal is checked and a low frequency circuit shapes the output pulse modulating the gate voltage. In this example, the input signal is a 10 μs pulse and the output pulse has a width of 6 μs modulating the gate to source voltage, avoiding the resonances of the internal matching networks of the amplifier.

Figure 10






















Scaled HPAG Transmitter Prototype

Finally, figure 11, shows a photograph of a scaled amplifier module as a previous step to the final HPAG design. The prototype consists of two BLA0912-250 amplifiers. The combination process is made with the “Bended Gysel” to which a λ/4 microstrip line (at the center of the MIDS Band) has been added. So, a balanced structure has been obtained. This feature is more than a necessity due to the poor input return losses characteristic of the amplifiers (between -5 and –9 dB in our frequency band).

Figure 12 shows the measurements made. Now, the input signal is more restrictive, pulses of 3ms of width with a duty cycle of 20%. During the pulse, the current is given by the capacitors placed near the drains of the amplifiers (2.5 mF for each LDMOS), which are recharged between the pulses. The power gain variation in saturation mode (40w of input signal) is around 1 dB in the frequency bandwidth with an output power of more than 325 Watts (335-390w).

In conclusion, it has been demonstrated the possibility of developing a Pulsed Solid-State Transmitter with LDMOS technology for long pulses and high duty cycles, an exclusive application for bipolar technology till now. Thanks to these new features, this technology can be used for developing MIDS transmitters, for that reason a scaled HPAG prototype has been presented and also the facility of developing a collector modulation for shaping the transmitted pulses.




















Figure 11.- Photograph of the HPAG Transmitter Prototype.



















Figure 12.- Output Power (dBm) of the HPAG Prototype with a duty cicle of 20% and pulse-width of 3ms.





Acknowledgements

To SILICA, Philips Spain Distributor for providing us the samples and the information about the amplifiers, and also, to CIDA and the Spanish Ministry of Science and Technology (TEC2005-07010-C02) for supporting this work.

1. E.D. Ostroff, M. Borkowsky Solid State RadarTransmitter Franklin Institute

2. A. Asensio, J. Tejerina 3.5KW RADAR TRANSMITTER FOR HIGH CAPACITY MODE S SYSTEMS Congreso: IEEE 2000 International Radar Conferenc, USA

3. BLA0912-250. Product Catalog. Philips

4. Gysel, U.H.; "A New N-way Power Divider/Combiner Suitable for High-Power Applications" Microwave Symposium Digest, MTT-S Internacional, vol. 75, nº 1 May , 1975

5. A.Asensio, M.Burgos. Spectral Distortion in Pulsed Class-C Amplifiers IEEE Transactions on Aerospace and Electronics Systems (AES). Vol 35, NO. 4 October, 1999.

BIOGRAPHIES:

Alberto Asensio López was born in Zaragoza, Spain, in 1960. He received the Ingeniero de Telecomunicación degree from the Technical University of Madrid, Madrid, Spain in 1984, and the Ph.D. degree at the Signals, Systems, and Radiocommunications Department of the Technical School of Telecommunication Engineering of the same University in 1990, where he has been Associate Professor since 1991. His research activities are in the area of high frequency circuit design and radar systems.

Address:
Alberto Asensio López
Universidad Politécnica de Madrid
E.T.S. INGENIEROS DE TELECOMUNICACIÓN Edif :C- Despacho 419
Ciudad Universitaria s/n
28040 MADRID (SPAIN)

Jose Luis Serrano was born in Madrid, Spain, in 1960. He is working towards the Ingeniero de Telecomunicación degree from the Technical University of Madrid, Madrid, Spain His research activities are in the area of high frequency circuit design, power amplifiers and radar systems.

Address: Jose Luis Serrano
Universidad Politécnica de Madrid
E.T.S. INGENIEROS DE TELECOMUNICACIÓN Edif :C- Despacho 407
Ciudad Universitaria s/n
28040 MADRID (SPAIN)

Javier Gismero Menoyo was Born in Madrid on November, 29th, 1960. He obtained his degree in Telecommunications Engineering in 1984, and PhD degree in 1989 ("Cum Laude" and Ph. D. extraordinary prize), both by the Polytechnical University of Madrid. Since 1986 he is member of the Microwaves and Radar Group (GMR) of the Telecommunications Engineering Technical School, at the Polytechnical University of Madrid. He is also professor at this University since 1989, in the general knowledge area of Signal Theory and Communications. His present research activities include high frequency device modelling and microwave circuits design, with special interest in low noise oscillators for wireless applications from L to Ka band (DECT, VSAT, LMDS) and radar systems. Also, he is involved in secondary radar systems design and evaluation with special enphasis on digital receiver techniques for ECM resistant transponders and interrogators. On the other hand is administrator of UNIX systems and is in charge of the GMR´ LAN (including web and ftp servers).

Address: Javier Gismero Menoyo
Universidad Politécnica de Madrid
E.T.S. INGENIEROS DE TELECOMUNICACIÓN Edif :C- Despacho 420
Ciudad Universitaria s/n
28040 MADRID (SPAIN)

Álvaro Blanco del Campo was born in León (Spain) in 1979. He received the Ingeniero de Telecomunicación degree, equivalent to M.S.E.E. degree, from Universidad Politécnica de Madrid (UPM), Spain, in 2002. Since February 2000 he has been part of the Microwave and Radar Group at the Departamento de Señales, Sistemas y Radiocomunicaciones (SSR), UPM, where he carried out his Master thesis on Thermal Characterisation of MMIC Power Amplifiers. Since October 2002, he has been working toward the Ph.D. degree at the SSR. His research activities and interest includes the design, developing and fabrication of High Range Resolution Radars and the characterisation of thermal problems arisen with the use of power amplifiers.

Address: Álvaro Blanco del Campo
Universidad Politécnica de Madrid
E.T.S. INGENIEROS DE TELECOMUNICACIÓN Edif :C- Despacho 419
Ciudad Universitaria s/n
28040 MADRID (SPAIN)

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