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A Digital Phase Detection Subsystem

A single-channel assembly for high-speed, high accuracy phase and amplitude measurements of an IF signal pair

A Digital Phase Detection Subsystem

Signal Technology Corp.,
Olektron Operation
Beverly, MA

The model IFS-9830 digital phase detection subsystem (DPDS) is a single-channel (one phase comparison) assembly used for high speed, high accuracy phase and amplitude measurements of an IF signal pair. The assembly measures the absolute phase difference between IF inputs and produces a representative eight-bit binary word at its output. Amplitude information for each IF input is presented as a video signal consisting of a compressed (logarithmic transfer) representation of the signal level. Figure 1 shows the functional block diagram of the DPDS.

The subsystem utilizes a monolithic constant phase logarithmic (MCPL) amplifier to process input signals over a wide dynamic range (60 dB or better). This amplifier is based on a patented application-specific IC and provides accurate amplitude detection while supplying a limited (fixed power level) IF output signal with nearly constant electrical length for driving a phase detector. This configuration facilitates the accurate measurement of the absolute phase difference between pairs of IF input signals. Figure 2 shows the measured phase deviation and logarithmic linearity of an MCPL amplifier over a –65 to 0 dBm input range.

The DPDS is an integration of advanced analog signal processing and digital technologies. The highly accurate digital output phase detection results from optimization of the internal IF, video and logic circuitry. Erasable programmable read-only memories (EPROM) are coded to reconstitute the phase information by calculating the arctangent of the inphase (I) and quadrature (Q) detection components. Error correction programming accommodates the inherent fidelity limitations resulting from the pseudosinusoidal output of the phase detection over a wide range of input conditions. Figure 3 shows a plot of the digitized phase error of two 160 MHz IF signals at various relative phase offsets.

Table I
Key Electrical Specifications

Center Frequency (MHz)


Operation Bandwidth (max) (MHz)


Input dynamic range (min) (dB)


Differential dynamic range (max) (dB)


Log video output (typ) (V)

0 to 1

Log linearity (max) (dB)

± 1

Phase range (")

0 to 360

Phase error absolute (")


Operating temperature range (° C)

-40 to +85

Supply power (V DC)

± 8 to ± 15 at 6 W (max)

The DPDS is designed to operate at 160 MHz with a 10 MHz operating bandwidth. Table 1 lists the unit’s key performance specifications. The ability to provide valid data in less than 50 ns allows the subsystem to be used in systems that require real-time data acquisition. The utilization of monolithic circuitry and high circuit density provides good performance within a minimal package outline. In addition, all major internal components are screened to MIL-STD-883 specifications and structured for rigorous qualification testing.

The DPDS is suitable for use in interferometry systems, direction-finding (phase and amplitude) applications, angle-of-arrival determination, instantaneous frequency measurements and test set applications. It is supplied in a 2.0" x 3.0" x 0.9" aluminum housing with SMA female IF input connectors and a multipin connector for DC power and data output. The subsystem’s price is $7500 each and delivery time is 18 weeks (ARO) for 10 units or less.

Signal Technology Corp.,
Olektron Operation,
Beverly, MA
(978) 922-0019.

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