An integrated passive device (IPD) technology has been developed in order to achieve lower cost, miniaturization and higher performance in RF and microwave devices applied to the front-end modules of wireless communication systems. Various kinds of high performance IPDs have been fabricated on a six inch GaAs wafer due to the well-developed, low cost RF passive manufacturing technology. Since this article is primarily about the practical design and fabrication of IPDs, it will discuss topics such as IPD fabrication technology, design flow, schematic circuit design and 3D EM simulation. Different kinds of IPDs such as baluns, power dividers, lowpass filters (LPF), and their measurement results are presented.

In the electrical device industry, there is a trend for the integration and miniaturization of electronic systems, while steadily increasing performance, reliability and yield and reducing cost. Owing to the fact that IPDs are generally fabricated using standard wafer fabrication technologies, such as thin film and photolithography processing, they can be manufactured with these advantages and widely used in front-end RF sections of the mobile phone, comparable to embedded passive devices in an organic substrate or in low temperature co-fired ceramic (LTCC) substrates.1

IPDs, which contain passive circuit components such as resistors, inductors and capacitors, are totally integrated and mounted on a semiconducting substrate.2-4 Through IPD technology, it is possible to integrate individual passive components into an RF device or system.5 IPDs can be applied to existing fields of applications, which use whole passive devices and have already been applied to the front-end modules of mobile systems. In mobile phone communication systems, many functional blocks, such as filters, baluns/transformers, diplexers, power combiners/dividers, and couplers can be realized by IPD technology.6-10 In addition, the application of IPD technology to semiconductor processing is fully compatible with existing active devices and, thereby ensures semiconductor processing compatibility.

IPD Design Flow

There is a certain design flow that has been developed in order to simplify the design of IPDs. Specific design flows may vary among designers but, in general, almost all design flows are similar. In order to meet performance and cost targets, a general design methodology should be followed. This consists of the following steps: Choose the optimum topology and the right components from the design cell library that match the selected technology, and then perform the design by using software, such as ADS or AWR for a circuit-level simulation and a physical layout that fits the available space. After the layout, an EM simulation employing software, such as CST, is performed in order to optimize the component interaction, the wire-bonding with the pads and the packaging. In the next step, the various devices are arrayed and the masks are made for aligning the patterning. The designed devices are then fabricated using the semiconductor manufacturing process. The fabricated wafer is then thinned, using a polishing process, sawn using an automatic dicing saw, and assembled by die-bonding, wire-bonding and the SOT packaging process. Finally, the IPDs are subjected to the measurement of their DC, RF and power performances.

Figure 1

Fig. 1 Cross-sectional view of the GaAs IPDs.

Advanced Fabrication Process of Integrated Passive Devices

High-quality GaAs substrates and passive integration technology, characterized by accurate NiCr thin film resistors (TFR), high Q-factor spiral inductors and high-yield metal-insulator-metal (MIM) capacitors, enable the realization of fully integrated passive functional blocks. The proposed process starts with a first passivation layer, which is composed of SiNx and is deposited by plasma-enhanced chemical vapor deposition (PECVD) up to a thickness of 2,000 Å. This layer is necessary to attain an even surface over the defects and roughness of the substrate surface. After SiNx deposition, an e-beam-evaporated NiCr layer is deposited from a target consisting of 90 percent Ni and 10 percent Cr, in order to get the optimal performance. A Ti/Au 200 Å/800 Å layer, sputtered prior to plating process, is then used in order to increase the metal adhesion to the substrate. In the next step, the wafer is masked by photo-resist to define the structures of the bottom metal layer. Then, a 4.5/0.5 µm-thick Cu/Au metal layer is formed by electroplating, which is used as the contact metal for the NiCr resistors, bottom metal layer for MIM capacitors, and metal feedline and coils for spiral inductors. Now the MIM capacitor middle dielectric part has to be realized, a SiNx layer, 2,000 Å thick is deposited by PECVD and masked to define the structure. After the deposition step, a reactive-ion etching (RIE) step in O2/SF6 is performed to remove the undesired layer of the SiNx. Next, a 1,000 Å-thick Ti/Au seed metal layer followed by an air-bridge post-photo process is deposited by sputtering. Then, an air-bridge photo process is performed prior to a Cu/Au (4.5 µm/0.5 µm) top metal definition and plating process, by which top metal and air-bridge are made for the capacitor, and air-bridge interconnections are formed at the coil paths around the metal feedline for the inductor. After the electroplating process, the air-bridge mask is stripped, and RIE of the Ti/Au seed metal is done. Finally, all components are passivated with a thickness of 0.3 µm SiNx to protect the components from oxidation and moisture. The cross-sectional view of the GaAs IPDs is depicted in Figure 1.

Figure 2

Fig. 2 Balun design using a transmission line (a) or lumped LCs (b).

Lumped L-C balun for WLAN Application

A balun provides balanced outputs from an unbalanced input. It is an important component in double-balanced mixers, push-pull amplifiers and the matching network placed between an antenna and the RF front-end system. Balanced output signals are defined as two output signals that have half of the input signal amplitude and are 180° out of phase.11-12 Generally, the easiest way to obtain a phase difference is by controlling the length of the transmission line. However, it requires a large length (λ/2) to achieve a phase difference of 180° at 2.4 GHz. An artificial transmission line can be used to provide a 180° phase shift in a small size by using lumped inductors and capacitors.13 This technique is used to convert the transmission line into lumped element circuits. A balun can be made using the relationship between the transmission line and the lumped element models, as seen in Figure 2. A compact 2.4 GHz wireless local area network (WLAN) balun designed and fabricated with a phase imbalance of less than 3° and very low insertion loss and high return loss is presented here.

Figure 3

Fig. 3 Measured S-parameters for the fabricated WLAN balun.

Figure 4

Fig. 4 Measured phase performance of the fabricated WLAN balun.

Figure 5

Fig. 5 Schematics of a typical power divider (a) and the designed DCS power divider (b).

After completing the layout, the circuit was fabricated using the GaAs IPD process created by NanoENS Co. Ltd. The fabricated chip was attached to the printed circuit board (PCB) using silver epoxy and bonded with gold wire. Measurements were then performed using a network analyzer over a frequency range of 100 MHz to 6 GHz. The insertion loss of the designed balun is affected by the core inductances of Lp and Ls; the design width of the core inductors is 15 µm. The balun was fabricated with a die size of 800 × 700 × 200 µm. Its RF performances are shown in Figures 3 and 4; the insertion loss and the return loss were below 0.25 dB and 25.75 dB, respectively. The phase imbalance was less than 3° and its amplitude imbalance was less than 0.5 dB.

Lumped L-C Type Power Divider for DCS Application

Power dividers are frequently used in transmitter and receiver systems, providing equal power division with an in-phase response. The power divider splits the input power into two or more output ports; it is a potentially lossless device, provided that no power is reflected from its output ports. Power dividers need to be matched at all ports; the output ports need to be isolated.14-15 A typical two-way power divider includes an isolation resistor (R = 2Z0) and two λ/4 transmission lines with an impedance of Z0, where Z0 is the characteristic impedance of the power divider. The schematic diagram of a typical two-way power divider is shown in Figure 5. The power divider circuit can be converted, as seen in the figure, by using the relationship between the transmission lines and the lumped element models. The inductance effects of the interconnections between the output ports and ground also need to be taken into account. For the bond-wire and bump inductance, the required inductance values are 0.36 and 0.02 nH, respectively. To be able to achieve low losses and a wide bandwidth, inductors with relatively high resonant frequencies and large Q-factors are required. A small 1.8 GHz digital cellular system (DCS) power divider with a very low insertion loss, a high return loss and good isolation was designed and fabricated.

Figure 6

Fig. 6 Measured insertion loss, return loss and isolation for the fabricated DCS divider.

After completing the layout, the circuit was fabricated using the GaAs IPD process. The final required R, L, and C values were determined after optimization. The fabricated DCS power divider, with a die size of 850 × 750 × 200 µm, and its RF performances are shown in Figure 6; the insertion loss is below 0.56 dB, the return loss is below 30 dB, and the isolation is better than 27.5 dB around the center frequency. The amplitude imbalance between the output ports is approximately 0.1 dB; the phase difference is 1° at the operating frequency.

Lumped L-C Type Lowpass Filter for WLAN Application

LPFs are an essential component in many electrical circuits for passing wanted signals and to eliminate or attenuate harmonics. The filter design starts from the synthesis of a standard third-order Butterworth LPF using lump elements.16 A shunt capacitor Cs is added to the inductor Ls in order to create a transmission zero at approximately 5.6 GHz. Since there is only one spiral inductor in this filter design, only one capacitor can be added to create one resonant transmission zero. The inductance is also adjusted to achieve a good input-matching in the passband. The schematic circuit and 3D structure of the designed LPF are given in Figure 7.

Figure 7

Fig. 7 Schematic of the designed WLAN LPF (a) and the CST simulation structure (b).

Figure 8

Fig. 8 Measured S-parameters for the fabricated WLAN LPF.

There are many differences found between the circuit level simulation and the EM simulation results. In order to minimize this gap, a circuit-tuning method using the internal ports is used in this LPF design.17 By using this optimization method, a response closer to the specifications was achieved. Figure 8 shows a photograph of the 2.4 GHz WLAN LPF with a die size of 660 × 400 × 200 µm. The insertion loss was typically 0.56 dB at 2.4 to 2.5 GHz, and the return loss was below 27 dB. The attenuation level in the second-harmonic frequency was less than -25 dBc.

Figure 9

Fig. 9 The SOT package schematic for the fabricated IPDs (a) full view, (b) side view, (c) top view and (d) front view.

SOT Packaging and Power handling Measurement

The use of semiconductor wafers is a cost-effective way to simultaneously fabricate many chips. Once all of the fabrication and testing is complete, the chips are separated from the wafer and assembled into the final integrated circuit (IC) package. The assembly and packaging process takes the approved electrical devices, places them in a package and interconnects the device bonding pads to the package leads. The packaging provides a means of protecting the chip from the environment and from handling damage, provides physical support for the chip heat dissipation, interconnection for the signals in and out of the chip, and for attaching it to a high assembly level.18 In this work, SOT packages were used for the fabricated IPDs, which are small in size and allow a higher board density, leading to a higher electrical speed for system applications. The SOT packages are of the cheap surface-mount plastic-molded type, with leads on their two longer sides in order to achieve a low cost and a low profile. The SOT package schematics are illustrated in Figure 9.

In general, power dividers and LPFs are usually located next to the power amplifier in order to split the power or remove the harmonic signals. Therefore, the power handling capacity is a very important factor in power dividers and LPFs. How to measure the power handling of the fabricated power dividers on the GaAs substrate will be shown as an example. Figure 10 shows the system used for the power divider’s power handling measurement. The incident power of the power divider can be measured by using a {20 dB coupler and the output power of the power divider by using a {40 dB attenuator and a spectrum analyzer. For the first test, 3.5 W of RF continuous wave power is injected into the input of the power divider. After 10 hours of operating time, the incident power is increased in 2 W steps. Due to its good thermal conductivity, the power divider on the GaAs substrate endured up to 12 W of incident power during the 60 hours step test. Figure 11 shows the measurement results of the power divider after the 12 W power handling tests.

Figure 10

Fig. 10 Measurement system for the power handling evaluation.

Figure 11

Fig. 11 Power handling measurement results.


The IPDs measurement data are compared with other literature for similar devices using the same frequencies. The IPDs fabricated in this work show the lowest insertion loss and the best return loss characteristics with the smallest die size. This data shows the best results for the designed IPDs compared to the other IPDs. Tables 1 and 2 show the WLAN balun, LPF and DCS power divider that were fabricated by NanoENS Co. Ltd.’s manufacturing process compared to other previously produced devices.

Table 1

Table 2


Compact-size RF IPDs were successfully fabricated on GaAs substrates with high power handling capability and low loss. The WLAN balun with a die size of 800 × 700 × 200 µm was fabricated, which showed an insertion loss of 0.25 dB and a return loss of 25.75 dB. The phase imbalance was measured to be less than 3°; the amplitude imbalance was less than 0.5 dB. The power divider for DCS application shows insertion loss of 0.56 dB, return loss of 30 dB, and isolation of 27.5 dB with a die size of 850 × 750 × 200 µm. An LPF is also fabricated for 2.4 GHz WLAN applications and has an insertion loss of 0.56 dB, a return loss of 27 dB and attenuation level at the second-harmonic frequency less than -25 dBc. The “cheap and compact” IPDs are achieved by using passive integration technology on GaAs substrates and SOT packaging method, while maintaining their high power handling capability and RF performances. Such IPDs are suitable for use in various handheld modules and system applications that require an effective cost, stringent size and high performance.



This research was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MEST) (No. 2011-0030819). This work was also supported by the Research Grant of Kwangwoon University in 2012.


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