The APLAC® world class, foundry-approved circuit simulation engine, is fully integrated into the AWR open design platform. The APLAC engine, which has been used in Nokia product development for more than 10 years, offers multi-level analyses (DC operation point, linear frequency domain, time domain, harmonic balance, phase noise, linear/non-linear noise including AC noise contributors, temperature), and accurate yield predictions. All algorithms support optimization and yield analysis (Monte Carlo) and there is support for multiprocessor platforms for harmonic balance (HB) analysis. The APLAC simulator delivers an enhanced harmonic balance method, which enables simulation of larger RFIC circuits for faster design time and less memory use. Also offered is the transient-assisted HB method (TAHB) for digital divider circuits, as well as accurate non-linear phase noise measurements, and a versatile simulation tool for analog and RF applications from the IC level up to the system level. APLAC native netlists for model creation purposes are also allowed in AWR XML libraries. With APLAC any type of models are easily developed using extensive programming capabilities of APLAC scripting language. Features: · DC operation point, linear frequency domain · time domain (transient) · harmonic balance · transient-assisted harmonic balance · phase noise · linear/non-linear noise including AC noise contributors · temperature and yield analysis (Monte Carlo)