A once highly manual process, circuit design has been transformed by the advent of electronic design automation (EDA) tools and modular design methodologies. Despite continuing advances in automation technologies, the demand for increasingly complex System-on-Chip (SoC) platforms has shown no sign of slowing. Today’s SoCs incorporate billions of transistors with miles of electrical wiring that are integrated within a tiny chip. This technological feat requires large teams and complex software. As a result, the cost of circuit design continues to skyrocket, narrowing the competitive field to large, multinational companies capable of keeping up with the demand for capital and skilled talent. As a consequence, it is becoming increasingly difficult for small entities as well as the DoD to leverage the high performance technology it needs to design complex circuits for defense applications.
Under DARPA’s Electronics Resurgence Initiative (ERI), research teams from academia, commercial industry and the defense industrial base have been selected to address today’s SoC design complexity and cost barriers. The goal is to create an environment that could catalyze the next wave of U.S. semiconductor innovation and broaden the competitive field for circuit design. As a part of the ERI Design research thrust area, the list of research teams selected to take on two new programs—the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program—include the University of California, San Diego; Northrop Grumman Mission Systems; Cadence Design Systems; Xilinx Inc.; Synopsys Inc.; University of Southern California; Princeton University; and Sandia National Laboratories.
The IDEA and POSH research teams were unveiled yesterday during the first annual DARPA ERI Summit in San Francisco, Calif. The three-day event has brought together hundreds of members of the electronics community to explore the future of the industry and the criticality of the sector in national security.
Announced initially in September 2017, IDEA and POSH are two of six ERI “Page 3” programs—so named for their adherence to the guidance shared by Gordon Moore on the third page of his seminal 1965 research paper that articulated the technology trend, which became known as Moore’s Law. Although Moore could not have foreseen the extent to which his observations on transistor scaling would be stretched, he predicted even then that newly designed automation procedures would be needed to lay out circuits too complex for manual design. In response, the ERI “Page 3” Design programs seek to answer this question: Can we dramatically lower the barriers to modern System-on-Chip design and unleash a new era of circuit and system specialization and innovation?
Through the creation of a software-based, completely automated physical layout generator and an open-source intellectual property (IP) ecosystem, the IDEA and POSH programs seek to usher in an era of the 24-hour design cycle for DoD hardware systems, shorten upgrade cycles and enable the proliferation of custom commercial and DoD-specific SoCs.
With the support of 11 research teams from across the electronics R&D community, the IDEA program aims to create a “no human in the loop” layout generator that would enable users with limited electronic design expertise to complete the physical design of electronic hardware within 24 hours. The software created under IDEA would be capable of automatically creating circuit design files ready for manufacturing, reducing design time from years to a single day. By applying machine learning methodologies, IDEA hopes to continuously evolve and improve the performance of the layout generator for digital circuits, mixed-signal integrated circuits (IC), systems-in-package (SiP) and printed circuit boards (PCB).
“Through the IDEA program, DARPA aims to eliminate the DoD's resource and expertise gap associated with custom electronic hardware design for the most advanced technologies by enabling full automation and applying machine intelligence,” said Andreas Olofsson, the Microsystems Technology Office program manager leading IDEA and POSH.
The research teams selected to participate in the IDEA program include:
- University of California, San Diego
- University of Illinois at Urbana-Champaign
- Princeton University
- The University of Utah
- Northrop Grumman Mission Systems
- University of Michigan
- Yale University
- Cadence Design Systems
- University of Texas at Austin
- University of Minnesota
- Purdue University
POSH, the second program under the ERI “Page 3” Design research thrust area, seeks to significantly reduce the effort required to start a new mixed-signal SoC design by building a foundation of verified IP building blocks with known functionality. Drawing from the best practices of the software design community, the POSH program is designed to create an open source (OS) SoC design and verification ecosystem that will enable the cost-effective design of ultra-complex SoCs. Although there are significant benefits to the reuse of IP blocks in circuit design, the current licensing model has limited the scope of reuse. To create a sustainable OS hardware ecosystem, researchers are tasked with developing the hardware assurance technology required to validate the quality of open-source, mixed-signal SoCs and develop the critical open-source IP components.
“To help democratize access to custom, high-performance SoCs, the POSH program seeks to develop a sustainable ecosystem of open-source IP and accompanying validation tools,” said Olofsson. “Through POSH, we hope to eliminate the need to start from scratch with every new design, creating a verified foundation to build from while providing deeper assurance to users based on the open source inspection process.”
The teams selected to take on POSH’s research challenges include:
- Xilinx Inc.
- Synopsys Inc.
- University of Southern California
- Princeton University
- University of Washington
- The University of Utah
- LeWiz Communications
- Brown University
- Sandia National Laboratories
- Stanford University
ERI is a five-year, upwards of $1.5 billion investment to jumpstart innovation in the electronics industry. To address the impending engineering and economic challenges confronting those striving to push microelectronics technology forward, DARPA is nurturing research in circuit design tools, advanced new materials, and systems architectures through a mix of new and emerging programs.