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Simulate EV12AQ600 ADC ESIstream Serial Interface


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5/13/22 to 5/22/22 12:00 pm

Event Description

Technical Education Webinar Series

Title: Simulate EV12AQ600 ADC ESIstream Serial Interface

Date: OnDemand

Sponsored by: Teledyne e2v Semiconductors

Presented by: Stéphane Breysse, Applications Engineer at Teledyne e2v Semiconductors

Learn how to simulate the EV12AQ600 ADC ESIstream serial interface using Vivado simulator and testbench available in each ESIstream package (KU FPGA, Versal ACAP…).

Learn about synchronization aspects and what the overall latency is made of.

Presenter Bio:
Stéphane is a senior applications engineer in charge of high-Speed data converters and of the ESIstream high speed serial interface protocol used on latest Teledyne e2v ADC and DAC since 2019. He is passionate about FPGAs and embedded systems on which he acquired a solid experience after working 10 years as an R&D engineer.

Stéphane graduated from Grenoble INP - ESISAR in France in 2010.

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