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Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3

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When

7/28/21 11:00 am to 7/28/21 12:00 pm EDT

Event Description

Technical Education Webinar Series

Title: Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3

Date: July 28, 2021

Time: 8am PT / 11am ET

Sponsored by: Avnet and Xilinx

Presented by: David Brubaker, Product Line Manager, Zynq Ultrascale+ RFSoC, Xilinx and Fred Kellerman, Wireless Communications FPGA System Architect, Avnet

Abstract:
Synchronizing data converters is critical for phased array and massive-MIMO applications, and effects like architecture, alignment, temperature, voltage and process can impact performance. In this webinar, we will review the Xilinx Zynq® UltraScale+™ RFSoC data converter structure and recent multi-tile synchronization characterization and performance. A design methodology using HDL Coder™ from MathWorks will be shown for custom implementations of multi-tile synchronization on the Xilinx ZCU208 evaluation kit.

Presenter Bios:
David Brubaker is the Product Line Manager for the Zynq UltraScale+ RFSoC at Xilinx, where he is responsible for managing the early phase of Zynq UltraScale+ RFSoC products, including NPI and customer engagements. David has held leadership, technical and marketing roles in several large companies focusing on 3G, 4G and 5G wireless infrastructure including FPGA, ASIC and ASSP solutions. Earlier in his career, he held RF and wireless engineering leadership positions in several companies. David is a member of the IEEE and holds a Master’s degree in Electrical Engineering from Santa Clara University and Bachelor’s degree in Physics from San Diego State University.

Fred Kellerman is a Wireless Communications FPGA System Architect for Avnet, where he is currently responsible for enabling the Mathworks HDL Coder workflow on various Xilinx based RFSoC development boards and Avnet XRF RFSoC SoMs. Prior to Avnet, Fred held various engineering positions for several decades in the Aerospace and Defense industry. He has worked on various multi-processor radios which utilized many different types of SoC, DSP, CPU and FPGA devices. He helped design and build some of today’s active MANET MILCOM radio communications systems. He has published multiple communications signal processing papers and worked with various teams to develop several US and worldwide communications system patents. Occasionally he adjuncts and teaches a Digital Wireless Communications course for the Electrical Engineering department at Rochester Institute of Technology. Fred has a Bachelor and Master of Science from RIT and is a member of the IEEE.

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