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System Design from Antenna to Digital with Zynq UltraScale+ RFSoC


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11/28/18 11:00 am to 11/28/18 12:00 pm EST

Event Description

Technical Education Webinar Series

Title: System Design from Antenna to Digital with Zynq UltraScale+ RFSoC

Date: November 28, 2018

Time: 8am PT / 11am ET

Sponsored by: Avnet and Xilinx

Presented by: Luc Langlois, Director, Engineering & Technology / DSP and Luke Miller, EW/ISR System Architect at Xilinx Inc.

The quest for increased bandwidth in latest generation wireless, radar, and other high performance RF applications poses new challenges in RF design, signal processing and system integration. With multi-channel direct RF-sampling data converters, Zynq® UltraScale+™ RFSoC allows designers to supersede the traditional analog heterodyne architecture with digital signal processing to create highly integrated, re-configurable solutions for true software-defined radio (SDR).

This webinar will explore the entire signal chain from antenna to digital with the Avnet Zynq UltraScale+ RFSoC Development Kit featuring Qorvo 2x2 LTE Band-3 RF front-end card. Advanced techniques for system-level modelling and simulation with tools from MathWorks and Xilinx will illustrate the design process of wireless communication systems with Zynq UltraScale+ RFSoC from concept to verification.

Main themes:

  • modern wireless system design using direct RF-sampling data converters
  • digital signal processing for software-defined radio
  • design tool automation
  • small cell wireless network densification in pre-5G/LTE-Advanced Pro (LTE-A Pro)

Presenter Bios:

Luc F. Langlois is director of Engineering & Technology at Avnet. He received his BSEE from École Polytechnique de Montréal in 1990 and also holds a B.Mus in music performance from Université de Montréal. He began his career at the Hydro Québec Research Institute, numerical analysis group from 1989 to 1993 designing power system models and load flow study tools. He was an independent engineering consultant during the Internet boom, focusing on digital audio before joining Memec-InSight as a Xilinx-dedicated field applications engineer in 2000. Present activities focus on Xilinx SoC-based development platforms for digital signal processing in wireless communication, embedded vision and artificial intelligence in collaboration with leading Avnet suppliers.

Luke Miller works closely with Xilinx product planners and customers to achieve product success and exclusive access to EW/ISR + FPGA+ DSP leadership. Math, algorithms, and DSP are Luke’s specialties and he regularly communicates to diverse audiences, from engineers to executives. Luke has held a variety of diverse engineering roles from ASIC design to the design and deployment of many RADAR systems. Luke is considered a thought leader and expert in the Realm of RADAR/EW and has been a contributor to many articles, webinars, publications and speaking events. Luke received his BSEE in Electrical Engineering from Clarkson University and holds patents in FPGA technology specifically addressing power and adaptive beam forming.

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